Impedance Calculator

Method, formulas and references

How the impedance is calculated

Closed-form formulas such as IPC-2141 are fits to a limited set of geometries. They lose accuracy for thin dielectrics, coated or trapezoidal traces and coupled pairs. This calculator solves the electrostatic field of the actual cross-section instead.

The cross-section is divided into a graded rectangular mesh, finest at conductor edges and dielectric interfaces. The solver then computes the Laplace equation ∇·(ε∇φ) = 0 with the traces held at a fixed potential and the planes grounded. The capacitance per unit length follows from the stored field energy. That calculation is repeated with every dielectric replaced by air:

For an edge-coupled differential pair the solver runs twice, using the symmetry plane between the traces. An electric wall gives the odd mode and a magnetic wall gives the even mode. Broadside pairs instead drive both vertically aligned traces explicitly, with opposite voltages for odd mode and equal voltages for even mode:

Broadside differential pairs

Broadside means the two traces sit on different copper layers. This model is a balanced shielded stripline: two ground planes, equal outer clearances, matching trace dimensions, mirrored etch and mirrored outer dielectric plies. The central dielectric can have a different Dk. S is the copper-to-copper vertical gap. Width solving changes both traces; spacing solving moves the upper trace and its ground plane together while preserving H and copper thickness.

Offset traces, unequal copper widths or thicknesses, asymmetric dielectrics, and unshielded broadside pairs are outside this model. The fabrication corner check varies both traces together and keeps the pair balanced; it does not model registration error or imbalance between layers.

Broadside tests check the odd-mode symmetry against an equivalent half-height stripline, homogeneous-dielectric scaling, the wide-trace parallel-plate limits for both modes, and mesh convergence. The coated-microstrip comparison below is a separate validation and does not establish broadside accuracy against commercial tools. See Polar application note 143 for the distinction between balanced and unbalanced pairs.

Planar resin-rich layer

The optional internal-layer model replaces a flat band from the trace bottom to T + R above it with the entered resin-region Dk. H and H2 keep their original meanings and the planes do not move. R is measured from the trace top, so the remaining upper dielectric is H2 minus R. A zero R still fills the space beside the copper with resin. Upper plies are split at that boundary; lower plies are unchanged.

This is an explicit dielectric geometry solved by the same field solver, not an empirical impedance correction. It supports single-ended and edge-coupled internal traces, including coplanar ground. Surface microstrip and broadside pairs are outside this option. The resin Dk is a fixed user input at the frequency of interest; it is not inferred from a laminate name or resin percentage. See the resin-rich layer guide for assumptions and references.

Width and spacing solves preserve the band. Height sweeps and fabrication-height endpoints scale R with H2 while keeping copper thickness fixed; Dk sweeps and endpoints scale every dielectric, including the resin region. No independent resin-process tolerance is inferred. Tests check equal-material limits, thin-layer convergence and the wide-strip parallel-plate limit. The coated-microstrip comparisons below do not establish accuracy for resin-rich layers on manufactured boards.

Validation

These results were compared with a commercial 2D field solver on solder-mask coated microstrip:

The automated tests also check the solver against Hammerstad–Jensen microstrip and Wheeler stripline formulas; both must agree within 2 %. Real boards vary more than that. Laminate εr depends on frequency and resin content, and etching changes the width, so fabricators quote impedance to ±10 % (±5 % on request).

Tips

The optional fabrication tolerance check solves every combination of the entered trace-width, dielectric-height, Dk and pair-spacing endpoints. It reports the lowest and highest solved impedance against the allowed band around the target. It is an endpoint screening estimate, not a statistical yield or a fabrication guarantee; thickness, etch, mask and coplanar-gap variations are held fixed. Ask the fabricator for realistic variation limits. Rogers explains how material and geometry variation affect impedance.

• Use the εr your fabricator quotes for the specific prepreg or core and the signal frequency, not the generic 4.5 for FR-4.
• Solder mask lowers the impedance of surface traces by a few ohms. Leave it switched on for outer layers.
• In a stripline, the prepreg and the core often have different εr. Enter them separately.

References

1. E. Hammerstad, Ø. Jensen, “Accurate Models for Microstrip Computer-Aided Design,” IEEE MTT-S Int. Microwave Symp., 1980.
2. H. A. Wheeler, “Transmission-Line Properties of a Strip Line Between Parallel Planes,” IEEE Trans. MTT, 1978.
3. B. C. Wadell, Transmission Line Design Handbook, Artech House, 1991.
4. H. Johnson, M. Graham, High-Speed Digital Design, Prentice Hall, 1993.