Guides›AC Coupling Capacitors on High-Speed Links: the Value for Every Interface

AC Coupling Capacitors on High-Speed Links: the Value for Every Interface

23 September 2026 · 7 min read · pcbplanner

A series capacitor on a high-speed pair looks like the most boring part on the board, and it is the one most often chosen wrong. The value is copied from another design, the package is whatever was in the library, and the schematic gives no hint that one interface forbids the part entirely while another fails compliance if its body is one size too large.

This guide collects what each specification actually requires, why the value has both a floor and a ceiling, and why the footprint matters more than the capacitance.

What the capacitor is there for

AC coupling lets the two ends of a link sit at different common-mode voltages. A transmitter built on one process drives a common mode its partner may not tolerate, and on a cable the two ends may not even share a ground. Blocking DC also lets a receiver detect whether anything is attached: USB 3.2 and PCIe both detect a partner by looking for the receiver's DC termination, which only works if the link is DC-isolated ^[3].

That is why the serial interfaces that cross a connector nearly all mandate it on the transmit side, and why the interfaces that stay on one board — DDR, MIPI, RGMII — do not use it at all.

The value, interface by interface

Interface	Series capacitor	Value
PCIe Gen 1 / Gen 2	Required, transmit pair	75–200 nF ^{[1, 2]}
PCIe Gen 3 and later	Required, transmit pair	The range changed at 8 GT/s ^[1]; vendors use 75–220 nF, typically 220 nF ^[7]
USB 2.0 High Speed	Not allowed	DC-coupled. An edge-rate capacitor is permitted, but everything at the driver must stay under 75 pF ^[4]
USB 3.2 Gen 1 / Gen 2	Required on every transmitter	75–265 nF. A receiver may be coupled too, but then the window is 297–363 nF ^[3]
SATA 3.0	Required from Gen 2i upward	12 nF maximum, and the specification advises against values under about 300 pF ^[5]
SGMII	Required on every connection	0.1 µF, in an 0402 package or smaller ^[9]
DisplayPort main link	Required	75–200 nF, 100 nF preferred ^[10]
HDMI (TMDS)	None	DC-coupled: the sink biases the pair through its 50 Ω pull-ups ^[11]
1000BASE-T (MDI)	None in series	The transformer isolates. Each PHY-side centre tap gets its own 0.1 µF to ground ^[12]
MIPI D-PHY	Never	A series capacitor destroys the single-ended low-power mode ^[13]
DDR4 / LPDDR4	None	Single-ended, referenced to VDDQ

Note how far apart SATA and USB sit: 12 nF maximum for SATA, 75 nF minimum for USB 3.2. A 100 nF part that is correct on a SuperSpeed pair is eight times the SATA limit. This is the single most common substitution error, and it happens because both links look identical on a schematic.

Why there is a minimum and a maximum

The capacitor and the line form a high-pass filter. Each line of the pair sees its own capacitor into a 50 Ω single-ended impedance, so the corner frequency is f = 1 / (2π · 50 Ω · C): about 32 kHz for 100 nF, 12 kHz for 265 nF, and 265 kHz for SATA's 12 nF ceiling.

The minimum protects the low-frequency end. Scrambled or 8b/10b-coded data still contains long runs of the same polarity, and if the corner creeps into that content the baseline wanders and the eye closes from the top and bottom. The maximum exists because the capacitor has to charge: USB 3.2 requires a coupled receiver to discharge to 500 mV within 250 ms, tested against a transmitter at its largest permitted capacitance ^[3], and a larger part is also a larger pad.

The package matters more than the value

At 2.5 GHz and above, the capacitor is not really a capacitor — it is a discontinuity with a value written on it. The pads are wider than the trace, and the reference plane beneath them adds capacitance exactly where the line should stay at 90 or 100 Ω.

The SATA specification is unusually blunt about this: bodies larger than 0603, it says, are likely to fail the return-loss requirement outright ^[5]. In practice:

0402 or smaller, and 0201 where the layout allows it; 0603 is the largest any of these documents tolerates ^{[5, 8]}.
Void the reference plane under the pads, 100 % of the pad area and at least two layers deep ^[8].
Both capacitors of a pair identical — same value, same package, same orientation, placed symmetrically. Rotating one of them relative to the other is enough to show up in return loss ^{[8, 10]}.
Keep the stub into the pad symmetrical and short; twenty mil of stub already reflects at these frequencies ^[7].

See what a wider pad does to the impedance of your pair →

Which side, and where

The capacitor belongs on the transmit side of each direction — that is what PCIe and USB both require ^{[1, 3]}. Where along the trace depends on what it is driving:

Chip to connector: next to the connector or the edge fingers ^[7].
Chip to chip on one board: as close to the receiver as possible ^[7].
USB Type-C with an orientation switch or alternate-mode mux: between the mux and the receptacle, so the mux operates inside the common-mode limits set by the local PHY ^[6]. The specification states this twice in consecutive paragraphs, which is a fair indication of how often it is got wrong.

Four ways to get it wrong

Coupling twice. An SFP cage already contains coupling capacitors on its SGMII pairs; adding your own puts two in series and halves the capacitance ^[9].
A SATA-sized part on a USB pair, or the reverse. 12 nF and 100 nF are both “the coupling cap” in a library, and only one is right for each link.
Coupling something that must not be coupled. A capacitor on a MIPI D-PHY lane breaks low-power mode; on HDMI it removes the bias the sink provides. If an HDMI redriver is used in AC-coupled transmit mode, it needs 85–253 nF and a 499 Ω pull-down to ground on each output between the capacitor and the receptacle ^[11].
Tying the Ethernet centre taps together. Each PHY-side centre tap needs its own 0.1 µF to ground; the common-mode voltage differs between pairs and with the speed mode ^[12].

Checklist

Check whether the interface wants a capacitor at all before placing one.
Take the value from that interface's own specification, not from the last design.
0402 or smaller, identical parts, symmetrically placed on both lines.
Reference plane voided under the pads, at least two layers deep.
Transmit side; at the connector for a cabled link, at the receiver for a chip-to-chip link.
On Type-C, between the mux and the receptacle.
Nothing else in series on the pair: no test points, no ferrites, no ESD parts in line unless the interface allows them.

Look up the coupling capacitor and the rest of the rules for your interface →

Tools used in this guide

Interface Design Rules – Impedance, skew, loss budget and length limits of PCIe, USB, Ethernet, HDMI, DDR and other interfaces, applied to a layer of your own stackup with the field solver.
Impedance Calculator – Single-ended and differential microstrip, coated and embedded microstrip, stripline and coplanar lines, solved with a 2D field solver.
Trace Loss (Insertion Loss) Calculator – Insertion loss in dB/in and over the full length: conductor loss with copper roughness and dielectric loss from the field solver, with laminate Dk/Df across frequency.