I²C Pull-up Resistors: When 4.7 kΩ Works and When It Does Not

4.7 kΩ is a component value, not an I²C design rule. On a lightly loaded line it can be suitable; on a larger Fast-mode bus it can be too slow. A smaller resistor speeds up the rising edge but increases the current each device must sink. Calculate both limits for SDA and SCL. ^{[1, 2]}

Why the resistance has two bounds

An open-drain driver actively pulls the line LOW. When every driver releases it, the pull-up charges the total bus capacitance. The LOW-voltage guarantee sets the minimum resistor; the permitted rise time sets the maximum. The familiar RC rise-time relation measures 30% to 70% of the supply:

Use the weakest guaranteed driver on that line, at your supply voltage and operating conditions. Mode-specific minimum rise time and bus-capacitance limits must also be checked; a passive resistor cannot fix an oversized bus by itself. ^{[1, 2]}

Worked example: 3.3 V, 200 pF, 400 kHz

TI’s Fast-mode example uses 3.3 V, 200 pF, a 0.4 V maximum LOW voltage and a 3 mA sink guarantee. The maximum 30–70% rise time is 300 ns. It gives R_P,min = 966.67 Ω and R_P,max ≈ 1,770.3 Ω. ^[1]

Check 1.5 kΩ against both limits and resistor tolerance →

With 1% tolerance, the nominal resistance must lie between R_P,min/0.99 and R_P,max/1.01, approximately 976.4 Ω to 1,752.8 Ω. The 1.5 kΩ part still fits. Its maximum-resistance rise time is approximately 256.7 ns. Supply, capacitance and device limits in this example stay fixed; use their worst-case bounds in a real design.

For the same 200 pF bus in Standard-mode, the 1,000 ns maximum rise time would permit the nominal 4.7 kΩ example, subject to the remaining device and timing checks. If capacitance falls to 50 pF, 4.7 kΩ instead gives about 199.1 ns and can meet the Fast-mode rise-time requirement. The useful resistor changes with the bus. ^[2]

Estimate capacitance on each line

Add every connected pin’s capacitance, the copper on every branch, cables, connectors, protection parts and level shifters. SDA and SCL can have different totals. The calculator’s optional estimator sums a trace model or known capacitance per length, pin capacitance, cable capacitance and extra capacitance. Enter maximum datasheet values where available. ^{[2, 3]}

Trace length alone is insufficient: width, dielectric spacing, dielectric constant and adjacent copper change capacitance per length. Use the geometry estimator for a preliminary value, or enter a known pF/cm value from a solver. A cable’s pF/m also needs its own specification. Keep the estimator disabled when you already have a total from measurement or simulation.

Enable the capacitance estimator and build a per-line budget →

Include module pull-ups already on the bus

Resistors fitted to multiple modules act in parallel. Three 4.7 kΩ pull-ups give 1,566.7 Ω, not 4.7 kΩ; six give 783.3 Ω. At 3.3 V and 0.4 V LOW, the latter asks for approximately 3.70 mA, exceeding the example’s 3 mA guarantee. More pull-ups can cure a slow edge and simultaneously invalidate the LOW-level guarantee.

Before choosing a resistor, count all fitted pull-ups and confirm the voltage they connect to is compatible with every pin. Check the actual LOW voltage and rise time on the assembled bus. These resistor calculations address electrical edges; protocol timing, buffers, level translation and wiring still need their own checks. ^{[2, 3]}

Tools used in this guide

• I²C Pull-up Calculator – Pull-up resistor range for Standard, Fast and Fast-mode Plus I²C from bus capacitance, rise time and device sink current.
• Impedance Calculator – Single-ended and differential microstrip, coated and embedded microstrip, stripline, coplanar lines and broadside differential pairs, solved with a 2D field solver.
• Logic-Level Compatibility Checker – Check worst-case VOH/VOL against VIH/VIL, static noise margins and receiver input-voltage limits.

Sources

1. Texas Instruments SLVA689, I2C Bus Pull-Up Resistor Calculation: resistance bounds and the 3.3 V, 200 pF Fast-mode example.
2. NXP UM10204, I2C-bus Specification and User Manual, Rev. 7: Standard/Fast/Fast-mode Plus electrical limits and bus capacitance.
3. Texas Instruments SLVA704, Understanding the I2C Bus: open-drain signalling and bus design considerations.

Related guides

• RC Filter Design: Choosing R and C for Low-Pass and High-Pass Filters
• Controlled Impedance Explained: Microstrip, Stripline and Solder Mask

Browse all guides

Guides explain published methods and data with their sources; check the values for your own design. Terms · Privacy

Back to contents