How to Choose a PCB Stackup (and What 1080, 2116 and 7628 Mean)
· 9 min read · pcbplanner
The stackup (the order and thickness of copper and dielectric layers) is decided before routing starts and is hard to change afterwards. It sets your trace widths, how well signals are shielded and how cleanly return currents flow. This guide covers the two decisions that matter most: which layer is which, and what dielectric sits under the outer layers.
Rule one: every signal layer next to a plane
High-frequency return current flows in the plane directly under the signal trace, as close to it as it can get [5, 6]. Give every signal layer an adjacent solid plane (usually ground), and the loop between signal and return stays small: lower inductance, less radiation, less crosstalk and a controlled impedance.
Common assignments:
| Layers | Arrangement (top to bottom) | Notes |
|---|---|---|
| 4 | Signal · Ground · Power · Signal | The standard 4-layer build. Put fast signals on the top layer, over the ground plane. |
| 4 | Signal · Ground · Ground · Signal | Both outer layers get a ground reference; power is routed as wide pours on the signal layers. |
| 6 | Signal · Ground · Signal · Power · Ground · Signal | Two outer and one inner signal layer, each next to a plane; the tool's default for 6 layers. |
| 6 | Signal · Ground · Signal · Signal · Ground · Signal | More routing, but the two inner signal layers are adjacent: route them at right angles to limit crosstalk. |
When a signal changes layers, its return current has to change planes too. Place a ground via next to the signal via so the return path stays short, and never route a fast signal across a split or slot in its reference plane.
What 1080, 2116, 3313 and 7628 mean
Prepreg and core are woven glass fabric impregnated with epoxy. The numbers are standard glass-fabric styles [1]: finer weaves are thinner and carry more resin, which has a lower dielectric constant than glass, so their Dk is lower. The same material (IPC-4101 FR-4 [2]) therefore has different Dk values depending on the style. For one common FR-4, the laminate maker's own table gives [3]:
| Glass style | Resin content | Pressed thickness per ply | Dk at 1 GHz |
|---|---|---|---|
| 106 | 71 % | 0.053 mm | 3.66 |
| 1080 | 64 % | 0.081 mm | 3.85 |
| 2313 / 3313 | 55 % | 0.105 mm | 4.09 |
| 2116 | 52 % | 0.123 mm | 4.17 |
| 7628 | 43 % | 0.199 mm | 4.40 |
Each fab uses its own resin contents, so check its stackup sheet for the exact values; the trend is always the same.
The outer prepreg decides your trace widths
For an outer-layer trace, the dielectric to the first plane is the prepreg under it. The trace width for a given impedance scales roughly with that thickness. On standard 4-layer, 1.6 mm FR-4 boards with 1 oz outer copper and solder mask, the field solver gives:
| Prepreg under L1 | Thickness | 50 Ω single-ended | 90 Ω differential (W / S) |
|---|---|---|---|
| 1080 | 0.076 mm | 0.12 mm | 0.125 / 0.19 mm |
| 3313 | 0.099 mm | 0.16 mm | 0.17 / 0.26 mm |
| 2116 | 0.116 mm | 0.19 mm | 0.20 / 0.31 mm |
| 7628 | 0.210 mm | 0.35 mm | 0.39 / 0.59 mm |
| 3 × 7628 | 0.646 mm | 1.17 mm | 1.31 / 1.97 mm |
Differential pairs here use a spacing of 1.5 × the width. A 0.12 mm trace can escape fine-pitch parts and connectors such as USB-C and M.2; a 0.35 mm trace often cannot. That is why impedance-controlled boards use a thin, fine-weave prepreg on the outside even when the total thickness is the standard 1.6 mm: the remaining thickness goes into the cores in the middle.
Let the Stackup Advisor rank stackups for your impedance targets →
Glass weave and differential skew
A coarse weave such as 7628 has visible bundles of glass with resin-rich gaps between them. If one trace of a differential pair runs over glass and the other over resin, the two see different Dk and arrive at different times. This “fibre-weave effect” can create picoseconds of skew per inch, which matters at multi-gigabit data rates [4]. Fine and spread-glass styles (1080, 1078, 1067, 2116, 3313) reduce it; routing pairs at a small angle to the weave is another mitigation described in the same study.
A practical order of decisions
- Count the signal layers you need, including the ones that must be next to ground (fast signals first).
- Pick the layer count and arrangement so every signal layer has an adjacent plane.
- Choose the outer prepreg for the trace widths your parts can escape (fine pitch → thin prepreg).
- Use your fab's standard stackups: they are cheaper and have measured Dk values.
- Calculate widths for each impedance on each layer, then order controlled impedance.
Browse and edit stackups in the Layer Stack Manager →
Tools used in this guide
- Stackup Advisor – Enter board thickness, layer count and impedance requirements; the field solver ranks every matching fab stackup and gives the trace widths.
- Layer Stack Manager – 178 fab stackups from 2 to 12 layers, editable, with any signal layer sent to the impedance calculator.
- Impedance Calculator – Single-ended and differential microstrip, coated and embedded microstrip, stripline and coplanar lines, solved with a 2D field solver.
- PCB Laminate Materials (Dk / Df) – Datasheet Dk and Df of FR-4, low-loss and RF laminates (Isola, Panasonic, Rogers, Shengyi…) at any frequency, plus solder masks and copper foil roughness.
Sources
- IPC-4412, Specification for Finished Fabric Woven from “E” Glass for Printed Boards, IPC.
- IPC-4101, Specification for Base Materials for Rigid and Multilayer Printed Boards, IPC.
- Shengyi Technology, S1141 line-up table CN-LU-2106-S03 (Dk/Df per glass style and resin content, SPDR method), 2021.
- J. Loyer, R. Kunze, X. Ye, “Fiber Weave Effect: Practical Impact Analysis and Mitigation Strategies,” DesignCon 2007.
- H. W. Ott, Electromagnetic Compatibility Engineering, Wiley, 2009 (return currents and plane assignment).
- E. Bogatin, Signal and Power Integrity – Simplified, 3rd ed., Prentice Hall, 2018.