SPI Timing Calculator

Method, formulas and references

Opposite-edge SPI read timing

For an ordinary read where MISO changes on one SCLK edge and is sampled on the opposite edge, half a clock period is available. Add the outgoing clock delay, peripheral clock-to-output maximum, MISO return delay, controller setup and timing reserve. Margin = 500 / fMHz − total delay in ns; the zero-margin frequency is 500 / total delay in MHz.

This extends TI's isolation-loop budget to include the entered device and board delays. It assumes a 50% duty clock before the reserve is applied. Check first-bit/CS timing, MOSI setup, hold time, loading and edge integrity separately. Devices that launch or sample differently require their own timing model. Zero total delay has no finite calculated ceiling.

Use Delay & timing for PCB propagation estimates and Signal termination for a source resistor calculation.

Data sources

1. Texas Instruments SLLA522 — SPI timing through digital isolation
   Figure 1-3: clock-to-MISO round-trip delay must fit within the available half-clock period. The calculator adds the entered peripheral clock-to-output, setup and reserve budgets.