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PCB Crosstalk and the 3W Rule: How Much Spacing Is Enough?

23 September 2026 · 7 min read · pcbplanner

The 3W rule means a centre-to-centre pitch of three trace widths. For two equal-width traces, that leaves an edge-to-edge gap of two widths. It is a starting point for reducing crosstalk, not a noise limit or a guarantee that a receiver will work. The distance to the reference plane, coupled length and edge speed also matter.^[1]

With 0.15 mm traces, 3W means 0.45 mm between the centres and a 0.30 mm copper clearance. This guide uses that geometry to show why the same routing rule can give different results on different boards.

Is 3W measured from the edges or the centres?

Call the trace width W, the edge gap S and the centre pitch P. For equal widths, P = W + S. The conventional 3W rule is P ≥ 3W, so S ≥ 2W. Always check the dimension arrows in a vendor guide: a requirement explicitly stated as three widths of clearance means S ≥ 3W, which is a larger gap.

For W = 0.15 mm	Gap S	Pitch P
3W centre pitch	0.30 mm	0.45 mm
3W edge clearance	0.45 mm	0.60 mm

The Crosstalk Calculator takes edge-to-edge spacing. Its sweep row labelled 2 W is therefore the conventional 3W centre-pitch case. Entering 3 W in the spacing field tests a centre pitch of 4 W.

What NEXT and FEXT measure

A switching trace is the aggressor; the neighbouring trace picking up noise is the victim. Near-end crosstalk (NEXT) is observed at the victim end beside the aggressor source. Far-end crosstalk (FEXT) is observed at the opposite end. The calculator solves the even and odd modes of the coupled cross-section to estimate both.^[3]

Its saturated NEXT coefficient is Kb = (Zeven − Zodd) / [2 × (Zeven + Zodd)]. NEXT initially increases with coupled length, reaching Kb × V when the round-trip propagation delay reaches the edge rise time. Shortening a long parallel run helps only after it is short enough to leave that saturated region.

FEXT depends on the difference between the even- and odd-mode propagation delays. Ideal homogeneous stripline gives equal modal velocities and cancels this component; microstrip generally does not. Real discontinuities, unequal dielectric regions and imperfect terminations can spoil that cancellation.

Same 3W spacing, three distances to the plane

These are calculated examples from pcbplanner, using bare microstrip with W = 0.15 mm, copper thickness 0.035 mm, S = 0.30 mm and dielectric constant 4.1. The parallel run is 50 mm, the aggressor swing is 3.3 V and the 10–90 % rise time is 100 ps. Only the dielectric height H below the trace changes.

H	S/H	NEXT	Noise
0.10 mm	3.0	2.48 %	82 mV
0.20 mm	1.5	5.88 %	194 mV
0.40 mm	0.75	11.60 %	383 mV

All three meet the same 3W rule. Moving the reference plane further away lets more of the field reach the neighbouring trace, and the estimated noise rises. These use the calculator's normal mesh and rounded results. The noise conversion assumes weak coupling and matched terminations; the more strongly coupled cases need particular care. This is a geometry comparison, not a pass/fail table.

Changing H also changes the line impedance. To compare manufacturable alternatives at a fixed impedance, redesign the width on each stackup and repeat the spacing check. A fixed-width comparison isolates one effect but does not complete that design.

Load the 0.10 mm reference-plane example →

Compare the same traces with the plane 0.40 mm away →

Why edge speed matters more than clock frequency

The coupling calculation takes rise time, not clock repetition rate. A slowly repeating signal can still have a fast edge. Use the relevant output transition time from the device model or measurement, including the selected drive strength and load.

In the first example the 50 mm section has about 283 ps of one-way delay. With a 100 ps edge, NEXT saturates after roughly 8.8 mm. Reducing the run from 50 mm to 25 mm therefore leaves saturated NEXT about the same, although it shortens the noise pulse and reduces the first-order FEXT amplitude. Reducing it to 5 mm takes NEXT below saturation, to approximately 46 mV in this model.

Check the shorter 5 mm parallel run →

Does the rule apply inside a differential pair?

The gap inside a differential pair is an impedance-design input. The clearance between that pair and another pair is an isolation requirement. Applying a generic 3W clearance inside the pair can change its differential impedance.

TI's high-speed layout guide gives its own pair-to-pair spacing and keep-outs, including a five-width spacing rule and larger clearance to clocks. Those are vendor layout recommendations for the interfaces covered by that document, not a universal replacement for a channel specification. Follow the applicable device guidance. ^[2]

The two-line Crosstalk Calculator models one aggressor and one victim. It does not solve the four-conductor coupling between two complete differential pairs. Use it for the two-trace comparison above; use a suitable multi-conductor model for pair-to-pair coupling.

A practical spacing check

Start with the device's routing requirements and an uninterrupted reference plane.
State whether the spacing is an edge gap or a centre pitch before entering it into the PCB rules.
Use the actual stackup, solder mask, coupled length, signal swing and rise time in the calculation.
Compare estimated noise with the receiver's available noise margin, allowing for other noise sources and modelling error.
If the margin is poor, try more clearance, a closer reference plane or a shorter shared run, then recheck impedance.

Check the trace impedance after changing the stackup →

Tools used in this guide

Crosstalk Calculator – Near- and far-end crosstalk between parallel traces from the field solver, with a sweep over the spacing (3W rule check).
Impedance Calculator – Single-ended and differential microstrip, coated and embedded microstrip, stripline and coplanar lines, solved with a 2D field solver.
Propagation Delay, εeff & Timing – Propagation delay, length matching from skew, rise time to bandwidth, critical length and wavelength.
Interface Design Rules – Impedance, skew, loss budget and length limits of PCIe, USB, Ethernet, HDMI, DDR and other interfaces, applied to a layer of your own stackup with the field solver.