Guides›PCIe Gen3 Routing on a Hobby Budget: Lessons from an M.2 NVMe Carrier Card

PCIe Gen3 Routing on a Hobby Budget: Lessons from an M.2 NVMe Carrier Card

· 10 min read · pcbplanner

An M.2 NVMe carrier card is a good first high-speed project: a PCIe x4 edge connector, an M.2 Key M socket, four differential lanes each way and a reference clock. There is no chip to configure, but every trace carries 8 GT/s, so the layout is the whole design. This guide collects what the PCI Express specifications and public layout guides actually say, and applies it to a standard six-layer, 1.6 mm FR-4 board with a thin 1080 prepreg on the outer layers.

The PCI-SIG specifications are available to members only; the numbers below are cited by document, section and table so you can check them against your own copy.

What “Gen3” means for the board

PCIe Gen3 runs at 8.0 GT/s with 128b/130b encoding: every 128 data bits carry a 2-bit sync header, instead of the 8b/10b encoding of Gen1 and Gen2 [1]. One bit lasts 125 ps, and the fundamental frequency of the fastest pattern (the Nyquist frequency) is 8 GT/s ÷ 2 = 4 GHz. The base specification specifies its calibration channels at 4 GHz too [1], so loss and impedance are evaluated at 4 GHz.

Impedance: 85 Ω, and why not 100 Ω

The card specification allows a data pair impedance of 70–100 Ω at 8 GT/s, on both the add-in card and the system board [2]. Its own test channels are built from 85 Ω traces, the M.2 connector is characterised at 85 Ω [3], and application notes from TI and Samtec recommend 85 Ω on add-in cards so that any card works in any slot [5, 7]. Some layout guides list 100 Ω or 95 Ω, but those tables are written for the PCIe ports of specific processors [4]. For a carrier card between a CEM slot and an M.2 socket, design for 85 Ω differential.

On the example board, the field solver gives (spacing 1.5 × width, 1 oz outer and ½ oz inner copper, solder mask on the outside):

Layer85 Ω pair (W / S)DelayLoss at 4 GHz
L1 / L6, microstrip over 0.076 mm 10800.147 / 0.22 mm5.8 ps/mm0.68 dB/in
L3, stripline0.145 / 0.22 mm6.8 ps/mm0.77 dB/in

The loss figures assume standard FR-4 (Df 0.015 at 1 GHz) and standard ED copper; with smoother reverse-treated foil the L1 figure drops to about 0.61 dB/in. Samtec quotes about 0.8 dB/in at 4 GHz for standard FR-4 [7], the same order of magnitude.

Calculate the 85 Ω pair on your own stackup →

Loss and length

The base specification does not give one loss number; channels are judged by simulation [1]. Commonly quoted Gen3 budgets allocate about 6.5 dB at 4 GHz to the add-in card out of a total of roughly 22–23.5 dB [5, 8]. The card specification also limits the data trace delay on an add-in card to 750 ps from the edge fingers[2]. On the example board that is about 129 mm of microstrip, and 6.5 dB of loss would allow over 9 inches of trace, so on a carrier card the 750 ps delay limit is the one that binds. A carrier with 50–80 mm lanes is well inside both.

Check the loss of your lanes at 4 GHz →

Skew

  • Within a pair (P to N): less than 5 mil (0.127 mm) of length difference on an add-in card, 10 mil on a system board [2]. At 5.8 ps/mm that is under 1 ps. Correct a mismatch close to where it happens, for example with a small bump right after a bend, not at the far end [4, 5].
  • Between lanes: the limit is loose, 0.35 ns on an add-in card [2], because every receiver deskews the lanes during link training [1]. Do not spend board space length-matching the four lanes to each other.

AC coupling capacitors

Each lane has series capacitors on its transmit pair only. For Gen3 the value must be 176–265 nF, narrower than the 75–265 nF allowed at 2.5 and 5 GT/s [1, 3]. Use 0402 or smaller, with identical parts and a symmetric placement on P and N, and remove the reference plane under the pads to reduce their capacitance [4, 9].

On a passive carrier card, check where these capacitors already are. The card specification puts the host's transmit capacitors on the system board, and the M.2 specification puts a pluggable module's transmit capacitors on the module [2, 3]. A carrier that only connects the two may therefore need none; adding another pair in series would halve the effective value (two 220 nF in series give 110 nF, below the 176 nF minimum). Compare with the reference design of an existing passive adapter before you decide.

Reference clock and sideband signals

  • The reference clock is 100 MHz HCSL [3, 6]. Route it as a differential pair; the card specification's clock timing assumes nominal 100 Ω pairs [2]. The card specification's clock budget assumes at most 4 inches of reference-clock trace on the card [2].
  • Spread-spectrum clocking is optional and down-spread only, 0 to −0.5 % [1, 2]; the receiver handles it, the layout does not change.
  • On the M.2 Key M socket (platform side): PERST# pin 50, CLKREQ# pin 52, PEWAKE# pin 54, REFCLK− pin 53, REFCLK+ pin 55. CLKREQ# and PEWAKE# are open-drain with pull-ups on the platform [3].

Pinout traps

  • TX and RX names swap between tables. The M.2 specification names pins from each side's point of view. On the platform table, pins 49/47 are PETp0/PETn0 (the host transmitter); the module table calls the same pins PERp0/PERn0 [3]. Connect host transmit to module receive and double-check every lane.
  • P and N may be swapped to avoid crossing a pair: every PCIe receiver must support polarity inversion on every lane [1, 2].
  • Lane order may not be reversed freely. Lane reversal is optional in the specification, so wire lane 0 to lane 0 unless both ends are known to support it [1, 2].

Vias and reference planes

  • Keep lanes on one layer where possible; every via pair costs in the order of 0.25 dB in corner cases [9].
  • Use the same number of vias on P and N, and remove unused inner pads on signal vias [4].
  • Put ground stitching vias next to every signal via pair so the return current can change planes; TI asks for them symmetrically within 200 mil [4].
  • Keep via stubs short: TI recommends back-drilling stubs longer than 15 mil [4, 5]. On a 1.6 mm board, routing on the outer layers and changing to the layer nearest the far side keeps stubs short without back-drilling.
  • Never route a lane across a split or slot in its reference plane.

Check a via pair's impedance and stub resonance →

Power

The M.2 socket supplies 3.3 V ±5 % on nine pins. A Key M module may draw up to 2.5 A (peak, averaged over 100 µs), and each power contact is rated 0.5 A continuous [3]. Size the 3.3 V copper for 2.5 A and place bulk and ceramic decoupling next to the socket.

Checklist

  1. 85 Ω differential on every lane, over a continuous ground plane.
  2. P/N matched within 5 mil; lanes not matched to each other.
  3. Data traces under 750 ps (about 129 mm of microstrip here) from the edge fingers.
  4. AC capacitors 176–265 nF on transmit pairs only, and none duplicated in series.
  5. TX and RX crossed correctly between host and module; lane order preserved.
  6. Ground stitching vias at every layer change; short via stubs.
  7. 3.3 V rated for 2.5 A at the socket.

Tools used in this guide

  • Impedance Calculator – Single-ended and differential microstrip, coated and embedded microstrip, stripline and coplanar lines, solved with a 2D field solver.
  • Trace Loss (Insertion Loss) Calculator – Insertion loss in dB/in and over the full length: conductor loss with copper roughness and dielectric loss from the field solver, with laminate Dk/Df across frequency.
  • Propagation Delay, εeff & Timing – Propagation delay, length matching from skew, rise time to bandwidth, critical length and wavelength.
  • Differential Via – Via-pair differential impedance through the plane clearance from a 2D field solution, antipad sizing for a target, stub resonance and delay.
  • Layer Stack Manager – 178 fab stackups from 2 to 12 layers, editable, with any signal layer sent to the impedance calculator.

Sources

  1. PCI-SIG, PCI Express Base Specification, Revision 3.0, 2010 (§4.2.2 encoding; §4.2.4.4 polarity inversion; §4.2.4.10.1 lane reversal; Table 4-18).
  2. PCI-SIG, PCI Express Card Electromechanical (CEM) Specification, Revision 3.0, 2013 (§2.1 reference clock; §4.7 routing requirements; §6.1).
  3. PCI-SIG, PCI Express M.2 Specification, Revision 1.1, 2016 (Tables 36, 38, 44, 46, 54, 55, 75; §6.8.2).
  4. Texas Instruments SPRAAR7J, High-Speed Interface Layout Guidelines, rev. 2023.
  5. Texas Instruments SNLA426, PCI Express layout application note, 2023.
  6. Texas Instruments SNAA386, Clocking for PCIe Applications, 2023.
  7. S. Krooswyk (Samtec), “Successful PCIe Interconnect Guidelines at 8, 16, and 32 GT/s,” 2021.
  8. Astera Labs, “PCI Express 5.0 Architecture Channel Insertion Loss Budget.”
  9. NXP (Philips) AN10373, PCI Express PCB routing guidelines, 2005.

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