Guides›Via Fence and Stitching Via Spacing: From λ/20 to Millimetres

Via Fence and Stitching Via Spacing: From λ/20 to Millimetres

26 September 2026 · 6 min read · pcbplanner

A via fence is a row of ground vias that acts as a wall. Placed along an RF trace, around a noisy circuit or along the board edge, it keeps fields from spreading sideways between the planes. Stitching vias do the same job across a whole board by tying the ground planes together. Both only work if the vias are close together compared with the wavelength, and the usual rules for "close" are λ/10 and λ/20.

This guide shows how to turn those rules into a via pitch in millimetres, then checks the result with two physical estimates: the resonance of the cells between the vias and the leakage through the gaps.

Step 1: the wavelength inside the board

λ = c / (f × √εr)

Use the highest frequency you need to contain: an RF band, a clock harmonic, or for digital edges the knee frequency 0.5 / tr. A 100 ps rise time gives 5 GHz.^[3] The fields between two planes are inside the laminate, so use its dielectric constant. For FR-4 with εr = 4.2:

Frequency	λ in FR-4	λ/10	λ/20
1 GHz	146.3 mm	14.6 mm	7.3 mm
2.4 GHz	61.0 mm	6.1 mm	3.0 mm
5 GHz	29.3 mm	2.9 mm	1.5 mm
10 GHz	14.6 mm	1.5 mm	0.7 mm

λ/20 is the common conservative choice and λ/10 is often accepted. Both are design guidelines rather than requirements of a standard. A surface microstrip has part of its field in air, so its wavelength is longer than this; using the laminate εr keeps the pitch on the safe side. ^[4]

Step 2: check the cells between the vias

f11 = c × √2 / (2 × s × √εr)

Two planes stitched on a square grid of pitch s form small cavities. Treating each row of vias as a wall, the lowest resonance of a cell is f11. Real via rows leak, so the true resonance is somewhat lower; keep it at least twice the highest frequency. ^{[2, 4]}

Pitch	Cell resonance	Gap (0.6 mm pads)	Leakage estimate at 5 GHz
1.5 mm	69.0 GHz	0.9 mm	30.5 dB
2 mm	51.7 GHz	1.4 mm	26.6 dB
3 mm	34.5 GHz	2.4 mm	21.9 dB
5 mm	20.7 GHz	4.4 mm	16.7 dB

At 5 GHz every pitch in the table keeps the cell resonance far above the operating frequency, even the 5 mm grid. Yet 3 mm is already just over λ/10 (2.9 mm), and 5 mm is well over it. The cell resonance is rarely what limits the pitch; the leakage through the gaps is.

Step 3: estimate the leakage through the gaps

SE ≈ 20 × log10(λ / (2 × L))

The space between two via pads behaves like a slot of length L. Ott's slot formula estimates how much it attenuates a field, and gives 0 dB when the slot is half a wavelength long. ^[1] The last column of the table uses the free-space wavelength, as the via stitching calculator does. Each halving of the gap adds about 6 dB, which is the practical argument for a tighter fence around a sensitive RF section. Treat these values as order-of-magnitude estimates: they assume a single slot in a perfect wall, and a fence has many slots in a row. ^[4]

Load the 5 GHz, 3 mm pitch example →

Why an unstitched board resonates

fmn = c / (2√εr) × √((m / a)² + (n / b)²)

A pair of planes with no stitching is a cavity the size of the board. For a 100 × 80 mm board in FR-4 the first resonances are at 731 MHz, 914 MHz and 1.17 GHz. Noise injected between the planes near those frequencies builds up and radiates from the board edges. ^[2] Stitching the planes together, and a via fence along the edge, split the cavity into cells whose resonances are far higher, as in the table above.

Fencing a trace

A fence along an RF or clock trace uses the same pitch rules, with a row of vias on each side. Keep the vias connected to every reference plane the trace sees: on a stripline, the fence ties the plane above to the plane below. If the fence copper or the vias are close to the trace, the line becomes a grounded coplanar waveguide and its impedance drops. Either keep the fence far enough away that the impedance does not change, or design the line as coplanar from the start.

Check the trace impedance with coplanar ground beside it →

Checklist

Find the highest frequency to contain: the RF band, a harmonic, or 0.5 / tr for digital edges.
Calculate λ in the laminate and pick a pitch between λ/20 and λ/10.
Confirm the via-grid cell resonance is at least twice that frequency.
Around sensitive sections, tighten the pitch until the gap leakage estimate gives the isolation you need.
Stitch along the board edge and across plane pairs, and check the effect of a trace fence on its impedance.

Tools used in this guide

Via Stitching & Via Fence Spacing – Stitching and fence via pitch from the wavelength (λ/10, λ/20), via-grid cell resonance, leakage between vias and plane-pair cavity resonances.
Impedance Calculator – Single-ended and differential microstrip, coated and embedded microstrip, stripline and coplanar lines, solved with a 2D field solver.
Propagation Delay, εeff & Timing – Propagation delay, length matching from skew, rise time to bandwidth, critical length and wavelength.

Sources

H. W. Ott, Electromagnetic Compatibility Engineering, Wiley, 2009, chapter 6: shielding effectiveness of apertures and slots.
M. Swaminathan, A. E. Engin, Power Integrity Modeling and Design for Semiconductors and Systems, Prentice Hall, 2007: the cavity model of a plane pair and its resonances.
H. Johnson, M. Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall, 1993: the knee frequency 0.5 / tr of a digital edge.
pcbplanner Via Stitching & Via Fence Spacing, Method, formulas and references: wavelength, via-grid cell resonance, plane-pair resonances and slot leakage.