Interface Design Rules

Method, formulas and references

What this page does

Every interface carries the rules its specification, or the chip vendor’s layout guide, lays down: the impedance a pair is built to, how closely its two traces must match, how much insertion loss the board may spend and where the coupling capacitors and ground vias belong. Those rules are written for a channel, not for your board, so this page applies them to one layer of your stackup.

1. The cross-section of the chosen layer comes from the stackup, with every prepreg and core ply keeping its own Dk.
2. The 2D field solver finds the trace width, and the pair spacing, that meets the impedance target of the interface, following your spacing rule and the fab minimums.
3. That geometry then goes through the loss model at the Nyquist frequency of the interface: conductor loss from the incremental-inductance rule, copper roughness from the foil you chose and dielectric loss from the Df of the laminate. This gives the loss per inch, the loss over your route and the longest route the budget allows.
4. Each skew limit is turned into a trace-length tolerance from the delay of that same line, which is why the tolerance on a stripline is tighter in millimetres than on a microstrip.

The loss figure covers the traces only. Connectors, vias, the package and the die take their share of the same channel budget, so leave margin: spending no more than about two thirds of the budget on board traces is a common working rule.

Use the impedance calculator to finish the geometry, trace loss to see the loss across frequency, and the stackup advisor when no layer of your stackup can carry the width an interface needs.

Data sources

1. PCI Express Card Electromechanical Specification Rev. 3.0 (July 2013)
   §4.7.7 intra-pair skew 5 mil on an add-in card and 10 mil on a system board; §4.7.8 trace impedance 68–105 Ω at 5 GT/s and 70–100 Ω at 8 GT/s, excluding vias, connectors and packages; §4.7.9 750 ps edge-finger delay; Table 4-5 lane-to-lane skew; §4.7.1 AC coupling on the transmit pair; §2.1.1 the 100 MHz ±300 ppm reference clock; §6 removal of the planes under the edge fingers. PCI-SIG membership is needed to download it.
2. PCI Express Base Specification Rev. 2.0 (December 2006)
   Table 4-9: AC coupling capacitor 75–200 nF, transmitter lane-to-lane skew, unit interval; Table 4-12 receiver skew; §4.3.7.1 spread spectrum, 0 to −0.5 % at 30–33 kHz.
3. TI SLAAE45 — Layout Guidelines for PCIe Gen 4 (September 2021)
   Table 2-1: Nyquist frequency per generation, 100 Ω ±5 % for Gen 1/2 and 85 Ω ±5 % for Gen 3/4, 5 mil intra-pair, no inter-pair requirement, AC coupling 75–220 nF, at most two vias per high-speed trace, via stubs under 15 mil.