Phase Noise to Jitter & Jitter Budget

Method, formulas and references

Phase noise and phase jitter

Oscillator data sheets give the single-sideband phase noise L(f) in dBc/Hz: the noise power in 1 Hz at an offset f from the carrier, relative to the carrier. It is half the spectral density of the phase fluctuation, L(f) = S_φ(f) / 2, because L(f) counts one sideband and the phase noise appears in both. The integrated phase noise over the band from f₁ to f₂ is

and the phase variance is the integral of S_φ, twice the integral of L. That is the factor of 2 in MT-008 Eq. 2 and in TI SBAA653:

σ is the RMS phase jitter: the time error of the clock edges against an ideal clock, in the band integrated. Always quote the band with the number.

Integration between the points

As in MT-008 the curve is taken as straight lines between the points on the log-log plot. A straight line of slope s dB/decade is a power law, L(f) = L₁ (f / f₁)^b with b = s / 10, so each segment integrates exactly:

The segment areas are added and converted with (1) and (2); equivalently the segment jitters add as root-sum-square, which is how MT-008 labels its examples. Points are sorted by offset. The curve is not extrapolated below the first point, because close-in noise rises towards the carrier. Above the last point the last level can be held flat to the upper limit, as AN279 does for a measured noise floor; the tool says so when it does.

Integration band

• 12 kHz – 20 MHz is the band telecom practice uses (AN-815) and many oscillator data sheets quote.
• For an ADC sampling clock MT-008 integrates from about 100 Hz (or the lowest offset given) to twice the clock frequency, the approximate bandwidth of the clock input; TI SBAA653 uses about 20 Hz to at least the sample rate, with twice the sample rate recommended.
• Serial-link reference-clock limits, such as those of PCI Express, are defined through the specification’s own jitter filter functions, so a brick-wall band only approximates them.

Phase jitter is not period jitter or cycle-to-cycle jitter. AN279 estimates period jitter by weighting S_φ(f) with 4 sin²(πfT₀) before integrating; this tool does not do that conversion.

ADC signal-to-noise ratio

Sampling a full-scale sine at f_in with an RMS timing error σ limits the SNR to

independent of the sample rate. The ADC’s aperture jitter t_a adds to the clock jitter as root-sum-square. The jitter limit and the converter’s own SNR combine on a power basis, SNR_T = −10 log₁₀(10^−SNR_j/10 + 10^{−SNR_ADC/10}) (TI SLWA034). The equivalent number of bits inverts the ideal-converter SNR, ENOB = (SNR − 1.76 dB) / 6.02 dB (MT-001). Rearranging (5) for σ gives the jitter a target SNR allows.

Jitter budget at a bit error ratio

Deterministic jitter (duty-cycle distortion, intersymbol interference, crosstalk, periodic jitter) is bounded and quoted peak-to-peak; the tool adds the terms linearly, which is the worst case. Random jitter is Gaussian and quoted RMS; independent sources add as root-sum-square (HFAN-4.3.0). A Gaussian has no peak, so its peak-to-peak value is taken at the probability the link may be wrong, the bit error ratio:

Q is found by inverting the complementary error function numerically: 7.034 at 10⁻¹², 6.706 at 10⁻¹¹, so 2Q = 14.069 and 13.412, the multipliers of Renesas AN-815 Table 1. Where a standard specifies its own multiplier, use that.

A receiver’s clock recovery follows slow jitter, so only jitter above its tracking corner closes the eye (HFAN-4.3.0 shows a 20 dB/decade high-pass at 625–637 kHz for gigabit Ethernet and Fibre Channel). Integrate the clock’s phase noise over that band before adding it to a link budget.

For the frequency accuracy of the clock rather than its jitter, see crystal load capacitors and ppm budget.

Data sources

1. ADI MT-008, Converting Oscillator Phase Noise to Time Jitter (W. Kester, Rev. A, 10/08)
   Eq. 1 jitter-limited SNR; Eq. 2 and 3 RMS phase jitter in radians and seconds from the integrated phase noise; integration by line segments, upper limit 2·fc and lower limit 100 Hz for an ADC clock. Figures 5, 7 and 11 (−67 dBc → 1 ps; 0.064 ps; 0.18 ps; 1.57 ps for the ADF4360-1) are reproduced by this tool’s tests.
2. Skyworks (Silicon Labs) AN279, Estimating Period Jitter from Phase Noise (Rev. 0.1)
   L(f) = Sφ(f) / 2; extending a measured noise floor to the upper limit; the −54.46 dBc → 2.663 ps example at 160 MHz (tested). Its period-jitter weighting is not implemented here.
3. TI SBAA653A, Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (April 2025)
   RMS phase jitter = √(2·10^(A/10)), jitter = that / (2π Fs); SNR_J = −20 log10(2π fin tJ); clock and aperture jitter combined as root-sum-square; integration from about 20 Hz to at least Fs, 2·Fs recommended.
4. TI SLWA034, Implementing a CDC7005 Low Jitter Clock Solution for High-Speed, High-IF ADC Devices (December 2004)
   §2: total SNR from the jitter SNR and the ADC’s own SNR on a power basis; 78.9 dBFS and 72.4 dBFS give 71.5 dBFS (tested).
5. ADI MT-001, Taking the Mystery out of the Infamous Formula “SNR = 6.02N + 1.76 dB”
   Eq. 9, SNR of an ideal N-bit converter for a full-scale sine over dc to fs/2; inverted here for the equivalent number of bits.
6. Renesas (IDT) AN-815, Understanding Jitter Units (Rev. A, 03/2014)
   TJ = DJ + RJ; Table 1 RMS-to-peak-to-peak multipliers N (= 2Q) from BER 10⁻³ to 10⁻¹⁶, all reproduced by the tests; the 12 kHz – 20 MHz telecom band.
7. Maxim HFAN-4.3.0, Jitter Specifications Made Easy (Rev. 1, 04/08)
   Random jitter sources add as RMS, and a peak-to-peak value at a BER is needed to add them to deterministic jitter (14.1 × RMS at 10⁻¹²); the receiver’s high-pass jitter weighting (637 kHz Fibre Channel, 625 kHz 1000BASE Ethernet).