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PCIe PCB Routing Guidelines: Impedance, Return Paths, Vias, Loss and Skew

Start PCIe routing with the channel, not a single length or spacing rule. Identify the generation, endpoints, connectors, reference planes and permitted loss. Then choose a controlled differential impedance, keep the return path continuous, minimise discontinuities and check the whole path at the relevant frequency. A layout rule from one device guide is not automatically a PCI-SIG requirement for every board. ^{[2, 3, 4]}

This guide is a board-layout checklist for PCIe Gen3–5. The Gen3 M.2 carrier-card example gives actual stackup, delay and loss calculations for one specific channel.

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What changes between Gen3, Gen4 and Gen5?

Generation	Rate	Unit interval	Nyquist frequency
Gen3	8 GT/s	125 ps	4 GHz
Gen4	16 GT/s	62.5 ps	8 GHz
Gen5	32 GT/s	31.25 ps	16 GHz

These are the PCI-SIG NRZ signalling rates; the Nyquist frequency is half the symbol rate. Higher frequency makes laminate loss, copper roughness, via stubs and connector launches more significant. It does not turn an old fixed trace-length limit into a universal new one. ^[1]

Set the impedance from the actual channel

Choose the differential target specified for your endpoint, connector and board role, then ask the fabricator for a stackup that can build it. The commonly used 85 Ω target is appropriate for many PCIe add-in-card and connector examples, including our Gen3 M.2 case, but it is not a substitute for the applicable design guide or channel specification. Check the whole route, including package breakout, AC-coupling pads, vias and connector launch. ^{[2, 4]}

Solve the pair width and gap on your stackup →

For routing rules, state whether a distance is edge-to-edge or centre-to-centre. Keep adjacent pairs and unrelated fast nets far enough away to control crosstalk, while preserving the pair's own gap for impedance. Our 3W spacing guide explains why a generic 3W rule is only a starting point.

Give the pair a continuous return path

Route over a solid reference plane. Do not cross a split or void without an engineered return path; the detour changes impedance and increases coupling. At a layer transition, place a nearby ground-return via that connects the relevant reference planes. If the reference changes from ground to power, a simple ground stitch may not complete the return path, so review the plane-pair decoupling and transition geometry. TI illustrates reference-plane void and via-placement effects in its Gen5 guide. ^[2]

Keep pair geometry symmetric through bends, pads and transitions. Prioritise avoiding a discontinuity over forcing exact trace lengths with dense serpentines.

Budget loss across the whole channel

At the generation's Nyquist frequency, count board traces on both ends, connectors, packages, AC-coupling pads and vias. A board calculator can estimate trace conductor and dielectric loss, but it cannot account for every connector or package. Obtain S-parameters or models for these parts and check the channel with the endpoint's compliance method when margin is tight. TI's Gen5 note treats laminate, humidity, temperature and copper construction as material contributors. ^[2]

Estimate trace loss at 4, 8 or 16 GHz →

Use vias deliberately and control stubs

Each signal via changes impedance; an unused barrel beyond the signal layer is a stub. Its resonance moves lower as it gets longer, so a through-via transition that is acceptable at Gen3 may be poor at Gen5. Keep layer changes few, choose the exit layer with stub length in mind and consider back-drilling where the channel analysis requires it. Pair the signal transition with a suitable return via and check that antipads do not cut a narrow corridor through the reference plane. ^[2]

Estimate differential-via impedance and stub resonance →

Place AC coupling on the transmitter pair

Each PCIe transmitter lane needs series AC-coupling capacitors. Use the value range and placement required by the generation, topology and component documentation; there is no one value to copy across all generations. Place both capacitors symmetrically and avoid large pads or long necks that form a local impedance step. TI's Gen5 guidance discusses pad size, nearby reference-plane voiding and placement relative to the receiver or connector for its channel. ^[2]

The capacitors on a connector board may already exist on the other side of the connector. Confirm which side owns the transmitter and avoid duplicating a coupling pair. The AC-coupling guide separates interface-specific values and placement.

Check skew against the endpoint requirement

Match the positive and negative traces of each pair within the applicable device or form-factor limit. Use propagation delay on the actual layers rather than assuming that equal millimetres always mean equal delay. Lane-to-lane skew is a different requirement; the receiver can deskew lanes, so do not add long meanders merely to make every lane identical. The Gen3 carrier example shows both checks for a real form factor. ^[4]

Convert skew allowance into route length →

Before sending the board out

Record the PCIe generation, endpoint and connector documents that set impedance, AC coupling, skew and channel limits.
Confirm the fabricator's final stackup, target pair geometry, copper profile and controlled-impedance tolerance.
Check reference planes, return vias, pair-to-pair spacing and transitions in the routed board.
Include trace, connector, package and via effects in the loss or S-parameter check at the relevant rate.
Review the finished channel with the device vendor's required simulation or compliance flow where applicable.

Open the PCIe interface-rule checker →

Tools used in this guide

Interface Design Rules – Impedance, skew, loss budget and length limits of PCIe, USB, Ethernet, HDMI, DDR and other interfaces, applied to a layer of your own stackup with the field solver.
Impedance Calculator – Single-ended and differential microstrip, coated and embedded microstrip, stripline, coplanar lines and broadside differential pairs, solved with a 2D field solver.
Trace Loss (Insertion Loss) Calculator – Insertion loss in dB/in and over the full length: conductor loss with copper roughness and dielectric loss from the field solver, with laminate Dk/Df across frequency.
Differential Via – Via-pair differential impedance through the plane clearance from a 2D field solution, antipad sizing for a target, stub resonance and delay.
Propagation Delay, εeff & Timing – Propagation delay, length matching from skew, rise time to bandwidth, critical length and wavelength.
Crosstalk Calculator – Near- and far-end crosstalk between parallel traces from the field solver, with a sweep over the spacing (3W rule check).

Sources

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