ADC Input Settling Checker

Check whether a source, optional RC input filter and SAR ADC sampling capacitor settle within the acquisition window.

Method, formulas and references

Method

The target is ½ LSB = V_REF / 2^N+1 for an N-bit converter. The entered worst-case voltage step is applied between a fully settled ADC-pin capacitor and the previous sample-capacitor voltage. With no external shunt capacitor, the remaining step decays with τ = (R_source + R_filter + R_ON) C_sample.

With a shunt capacitor, the calculator solves the two-node linear RC network during acquisition, including charge sharing through R_ON and recharge through the source/filter resistance. It finds the minimum acquisition time for the sample-capacitor error to fall below ½ LSB. A divider's source resistance is R_top ∥ R_bottom.

If recovery is enabled, the ADC-pin error at the end of acquisition is allowed to decay through (R_source + R_filter) C_filter after the switch opens. This is a separate first-order check, not a full repeated-sample simulation. The model assumes an ideal source behind its entered resistance and does not include amplifier slew/settling, switch charge injection, leakage, input protection, noise, aliasing or a non-linear sampling switch. Check the chosen ADC's datasheet input model and timing.

References

Texas Instruments SBAA178, Determining Minimum Acquisition Times for SAR ADCs, input RC network and sample-capacitor settling.
Texas Instruments SPRACZ0, Charge-Sharing Driving Circuits for C2000 ADCs, charge sharing, filter capacitance and acquisition limits.

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