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Is USB 3 85 Ω or 90 Ω? What the Specifications Actually Say

23 September 2026 · 6 min read · pcbplanner

Search for the impedance of a USB 3 pair and you will find both 85 Ω and 90 Ω, each stated as if it were the obvious answer. Both numbers are real and both come from USB-IF documents — they simply describe different parts of the link.

Route your board to 90 Ω differential. 85 Ω is the target for the mated Type-C connector and the reference impedance the Type-C S-parameters are normalised to, not a trace specification.

Where each number comes from

Value	What it applies to	Document
72–120 Ω	The silicon: transmitter and receiver DC differential impedance	USB 3.2, Tables 6-18 and 6-22 ^[1]
85 Ω	The impedance all Type-C S-parameters are normalised to	Type-C R2.0 §3.7 ^[2]
85 Ω ± 9 Ω	The mated connector, measured with a 40 ps edge	Type-C R2.0 §3.7.3.1 ^[2]
90 Ω ± 5 Ω	The raw cable (45 Ω ± 3 Ω single-ended for coaxial construction)	Type-C R2.0 §3.7.1 ^[2]
75–105 Ω	The mated legacy USB 3.0 connector, including its PCB footprint	USB-IF connector whitepaper ^[3]
90 Ω nominal	The design target for the link as a whole	USB-IF connector whitepaper ^[3]
90 Ω ± 10 % / ± 15 %	PCB traces, as chip vendors specify them	Genesys Logic ^[6], TI ^[4]

So the trace number that USB-IF itself states is 90 Ω: “USB 3.0 specification defines a 90-ohm nominal characteristic impedance. If every component in the SuperSpeed link is designed with a 90-ohm impedance, there won't be any reflection” ^[3]. The 85 Ω figure only ever appears attached to the connector or to the S-parameter reference.

One wrinkle worth knowing: some SoC vendors publish their own number. TI's layout guidelines use 90 Ω on older devices and 95 Ω on newer ones, with a ±5 % window^[5]. If your controller's datasheet states an impedance, follow it — it describes that device's package and receiver.

How much does the difference actually cost?

The interesting part is how small this argument is. A trace at 90 Ω meeting a connector at 85 Ω produces a reflection of

Γ = (85 − 90) / (85 + 90) = 0.029, which is −31 dB of return loss.

Put next to the other discontinuities on the same link:

Discontinuity	Return loss
90 Ω trace into an 85 Ω connector	−31 dB
A 90 Ω trace built 10 % low by the fabricator (81 Ω)	−26 dB
A trace that arrives at 75 Ω	−21 dB
A connector launch with no plane voiding, sinking to 40 Ω ^[3]	−8 dB

Your fabricator's ±10 % tolerance moves the impedance further than the entire 85-versus-90 question, and a badly voided connector footprint moves it twenty decibels further again. Which is to say: pick 90 Ω, then spend your attention on tolerance and on the launch.

Design a 90 Ω pair on your stackup and see the tolerance →

What actually decides whether the link passes

USB 3.2 gives an informative budget of 8.5 dB for a host or device and 23 dB for the whole channel, at 2.5 GHz for Gen 1 and 5 GHz for Gen 2 ^[1]. Against that:

The connector launch. Without ground voiding under the receptacle pads, the launch impedance can fall to about 40 Ω — the whitepaper calls the voiding imperative^[3].
The coupling capacitors. Mandatory on every transmitter, 75–265 nF, and no larger than 0603 — TI asks for 0402 or smaller with the plane voided under the pads^{[1, 4]}.
Via stubs. Keep them under 15 mil or back-drill them; at 5 GHz the stub costs more than the via ^[4].
Loss. On ordinary FR-4 a Gen 2 pair spends roughly 0.7 dB per inch at 5 GHz, so a long run eats the budget before anything else does.

The rest of the rules, briefly

Intra-pair matching: about 5 mil, or 15 ps per metre. The specification sets no board limit; the raw cable is held to 10 ps per metre ^{[2, 4]}.
Pair-to-pair: no requirement at all. The transmit and receive pairs do not have to be the same length ^[4].
Polarity: the two lines of a pair may be swapped to avoid a crossover ^[4].
Spacing: five trace widths between pairs, 30 mil to any other signal, 50 mil to a clock ^[4].
Reference: one solid ground reference end to end, with stitching vias within 200 mil of every layer change ^[4].

Checklist

Design the traces to 90 Ω differential, ±10 %, unless your controller's datasheet states otherwise.
Treat 85 Ω as the connector's number, not the trace's.
Void the reference plane under the receptacle pads and under the coupling capacitors.
Coupling capacitors 75–265 nF, 0402 or smaller, on the transmit pairs.
Match within a pair to about 5 mil; ignore matching between pairs.
Keep via stubs under 15 mil, and ask the fabricator for controlled impedance rather than hoping.

Check a USB 3.2 pair against every rule on your own stackup →

Tools used in this guide

Interface Design Rules – Impedance, skew, loss budget and length limits of PCIe, USB, Ethernet, HDMI, DDR and other interfaces, applied to a layer of your own stackup with the field solver.
Impedance Calculator – Single-ended and differential microstrip, coated and embedded microstrip, stripline and coplanar lines, solved with a 2D field solver.
Stackup Advisor – Enter board thickness, layer count and impedance requirements; the field solver ranks every matching fab stackup and gives the trace widths.