Controlled Impedance Explained: Microstrip, Stripline and Solder Mask
· 8 min read · pcbplanner
“Controlled impedance” appears on fab order forms and in every high-speed layout guide, yet it is often treated as a checkbox. This guide explains what the impedance of a trace is, when it matters, and which details of the cross-section move it by several ohms. The numbers come from the 2D field solver in the impedance calculator, so you can reproduce each one.
What trace impedance is
A trace over a ground plane is a transmission line. It has an inductance L and a capacitance C per unit length, and a signal edge travelling along it sees a characteristic impedance Z0 = √(L/C) [1, 3]. Wider traces and thinner dielectrics add capacitance and lower Z0; narrower traces and thicker dielectrics raise it. The value does not depend on the trace length.
Wherever the impedance changes (a connector, a via, a different width, the receiver), part of the edge is reflected. The fraction is the reflection coefficient Γ = (Z2 − Z1) / (Z2 + Z1) [3]. A 60 Ω section in a 50 Ω system reflects 10/110 ≈ 9 % of the voltage; a trace at the edge of a ±10 % fab tolerance (55 Ω) reflects about 5 %. Reflections close the eye of a high-speed link and cause ringing on clocks.
When a trace needs controlled impedance
What matters is the rise time of the signal, not its clock frequency. A common rule of thumb is that a trace behaves as a transmission line once its delay exceeds about one sixth of the rise time [1]. On a surface microstrip over a thin 1080 prepreg, the signal travels at about 6.0 ps/mm:
| Rise time | Distance the edge travels | Critical length (1/6) |
|---|---|---|
| 1 ns (older logic, slow edges) | 167 mm | ≈ 28 mm |
| 100 ps (USB 3, PCIe, DDR) | 17 mm | ≈ 2.8 mm |
Modern I/O drivers switch in tens of picoseconds even when the data rate is modest, so almost every trace to a fast interface is “long” and must match the impedance the interface is specified for: typically 50 Ω single-ended, and 85, 90 or 100 Ω differential.
Work out the critical length for your rise time →
Microstrip and stripline
A microstrip is a trace on an outer layer with a plane underneath. Part of its electric field is in the air above, so the effective dielectric constant is lower than the laminate's and signals travel faster. A stripline is an inner-layer trace between two planes, with its field entirely inside the laminate.
A 50 Ω trace on the two layer types of the same six-layer, 1.6 mm FR-4 board (1080 prepreg on the outside, 1 oz outer and ½ oz inner copper):
| Layer | Dielectric to plane | Width for 50 Ω | Delay |
|---|---|---|---|
| L1, microstrip with solder mask | 0.076 mm, Dk 3.91 | 0.119 mm | 6.0 ps/mm |
| L3, stripline (asymmetric) | 0.092 mm below, 0.6 mm above | 0.121 mm | 6.8 ps/mm |
The practical differences:
- Crosstalk. In a stripline surrounded by one uniform dielectric, the even and odd modes travel at the same speed, so far-end crosstalk between parallel traces ideally cancels [1, 2]. On microstrip it does not, and it grows with the parallel length.
- Shielding. Striplines are enclosed by planes and radiate far less; microstrips are exposed.
- Speed and loss. Microstrip is faster (lower effective Dk) and slightly lower in dielectric loss because part of the field is in air.
- Access. Microstrip needs no vias to reach surface-mount pins; every via on a fast signal adds a small discontinuity and, on thick boards, a resonant stub.
Solder mask lowers the impedance
Solder mask is a dielectric (Dk around 3.5–4) that fills the space around an outer trace, where there would otherwise be air. It adds capacitance, so it lowers the impedance. On the 1080-prepreg microstrip above (0.0764 mm, Dk 3.91), the field solver gives:
| Trace width | No mask | With mask (30 µm, Dk 3.8) |
|---|---|---|
| 0.12 mm | 53.4 Ω | 49.9 Ω |
| 0.13 mm | 51.3 Ω | 48.1 Ω |
| 0.14 mm | 49.4 Ω | 46.3 Ω |
That is about 3.5 Ω, or 7 %, which is most of a typical ±10 % fab tolerance. A trace designed for 50 Ω without mask (about 0.137 mm here) ends up near 47 Ω on a real, masked board. Always design outer layers with the mask included; fabricators' impedance calculators do the same.
Etching and copper thickness
Etched traces are trapezoidal: the top is narrower than the bottom, by roughly 0.5 mil (12.7 µm) on 1 oz copper. All numbers in this guide include that etch. Thicker copper adds side-wall capacitance and lowers the impedance slightly. Fabs adjust the final width to their own etch process when you order controlled impedance, which is one reason to let them tune it rather than fighting over the third decimal.
Formulas versus a field solver
Closed-form equations such as IPC-2141 [5] or Hammerstad–Jensen [4] are fits to limited ranges of geometry. For the uncoated 0.12 mm trace above, Hammerstad–Jensen gives 54.6 Ω against the solver's 53.4 Ω, about 2 % high. That is still good, but these formulas have no term for solder mask, embedded traces or mixed dielectrics at all, and the older IPC-2141 microstrip formula is known to lose accuracy on thin dielectrics [2]. A 2D field solver computes the actual cross-section; the one in pcbplanner agrees with a commercial solver within about 1 % on coated microstrip [6].
Checklist
- Find the impedance your interface requires (50 Ω single-ended; 85, 90 or 100 Ω differential).
- Use your fab's actual stackup: the prepreg thickness and Dk under the outer layer set the width.
- Include solder mask for outer layers and the etch for all layers.
- Keep every impedance-controlled trace over a continuous reference plane: no splits or slots underneath.
- Order controlled impedance and give the fab the target and tolerance; they will fine-tune the width.
Calculate your trace width with the field solver →
Tools used in this guide
- Impedance Calculator – Single-ended and differential microstrip, coated and embedded microstrip, stripline and coplanar lines, solved with a 2D field solver.
- Propagation Delay, εeff & Timing – Propagation delay, length matching from skew, rise time to bandwidth, critical length and wavelength.
- Crosstalk Calculator – Near- and far-end crosstalk between parallel traces from the field solver, with a sweep over the spacing (3W rule check).
- Trace Loss (Insertion Loss) Calculator – Insertion loss in dB/in and over the full length: conductor loss with copper roughness and dielectric loss from the field solver, with laminate Dk/Df across frequency.
Sources
- H. Johnson, M. Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall, 1993.
- E. Bogatin, Signal and Power Integrity – Simplified, 3rd ed., Prentice Hall, 2018.
- D. M. Pozar, Microwave Engineering, 4th ed., Wiley, 2012 (transmission-line theory, reflection coefficient).
- E. Hammerstad, Ø. Jensen, “Accurate Models for Microstrip Computer-Aided Design,” IEEE MTT-S International Microwave Symposium Digest, 1980.
- IPC-2141A, Design Guide for High-Speed Controlled Impedance Circuit Boards, IPC, 2004.
- pcbplanner impedance calculator: method and validation against a Polar SI9000 field solver (within 1 % on coated microstrip).