Glass Weave Skew: How Much It Costs a Differential Pair, and How to Avoid It

Glass-weave skew is the delay difference between the two traces of a differential pair when one runs over glass yarn and the other over resin. In Intel’s measurements the worst case was about 16 ps per inch (0.63 ps/mm), against a PCIe intra-pair routing rule of 5 mil, which is under 1 ps ^{[1, 2]}. At 16 GT/s and above, a few centimetres of unlucky alignment can use the whole skew budget, so the fix is the laminate and the routing angle, not length tuning. This guide gives the formula, the length at which weave skew alone reaches a typical budget at each data rate, a worked PCIe Gen 4 example, and what each mitigation is worth according to published data.

For what the glass style numbers mean and how resin content sets a ply’s Dk, see the prepreg glass styles guide.

Where the skew comes from

E-glass has a dielectric constant of about 6 and epoxy about 3 ^[4]. A laminate is a woven glass fabric filled with resin, so the local Dk under a trace depends on whether it runs along a yarn, between yarns or over a crossing. The higher the Dk, the slower the signal, so the trace over glass arrives later than the trace over resin ^[1]. TI notes that the effect shows up in the differential S-parameters from about 2 GHz, that it varies from board to board, and that this variance makes it hard to diagnose ^[4].

Skew between D+ and D− turns part of the differential signal into common mode. That closes the eye at the receiver and adds to EMI ^{[1, 3]}.

The formula

Δt / L = (√Dk_max − √Dk_min) / c

This follows from the delay of a line, t_pd = √Dk / c ^[1], applied to two traces that see different Dk over the same length L. With c in the units used here, 1 / c = 3.336 ps/mm (84.7 ps/in). For a stripline, Dk is the laminate value; on a microstrip it is the effective Dk of laminate, mask and air ^[1], so less of the field sees the weave.

Which Dk values to use. Simonovich proposes taking the lowest-Dk prepreg of a material family (106, the most resin-rich) as Dk_min and the highest (7628, the most glass-rich) as Dk_max, from the laminate maker’s tables ^[1]. Across the material families he analysed, the mean difference was 0.72 with a 3-sigma tolerance of 0.09, so at most about 0.81, which agrees with the 0.8 Intel derived from its measurements ^[1]. His FR-4 example uses Dk_min = 3.30 and Dk_max = 4.02 ^[1]:

(√4.02 − √3.30) × 3.336 ps/mm = 0.628 ps/mm = 16.0 ps/in

That matches the measurements. Intel compiled more than 58,000 TDR and TDT measurements on hundreds of test boards from different laminates and fabricators. The mean differential skew was 3.85 ps/in with a standard deviation of 4.15 ps/in, so 99.7 % of values were within 16.3 ps/in, and Intel set its cut-off at 15 ps/in ^{[1, 2]}. The mean is small; the problem is the tail.

Delay per mm at Dk 3.30 in the Propagation Delay tool →

The same at Dk 4.02: the difference is the worst-case skew per mm →

It shows up as a notch in insertion loss

A pair with a total skew Δt has a null in its differential insertion loss at f₀ = 1 / (2 × Δt), with odd harmonics above it ^[1]. Simonovich’s simulation of 8.6 in at Dk 3.30 / 4.02 put the null at 3.6 GHz, with harmonics at 10.8 and 18 GHz ^[1]; the formula above gives 137 ps over that length and 3.64 GHz. Note what the formula implies: when the skew reaches one unit interval (UI), the null lands exactly on the Nyquist frequency, 1 / (2 × UI). In the PCIe Gen 2 simulation of the I-Connect007 article, at 16 ps/in the eye started to degrade at 5.6 in and was fully closed at 12.7 in, where the null reached the 2.5 GHz Nyquist frequency ^[3].

How long a pair can be at each data rate

Simonovich budgets 0.21 UI for intra-pair skew in his PCIe CEM Rev. 2.0 case study, taken from the PCIe external cabling specification, and concludes it is a reasonable figure ^[1]. The table applies that budget to faster rates. It is a planning number, not a specification: your receiver and channel decide the real margin.

The 5 GT/s row reproduces Simonovich’s result that a pair can exceed 42 ps after only 2.6 in ^[1]. The spread-glass column uses the worst-case skew that Dudek, Kuhn and Goldman predicted for a 100 Ω pair on spread 1080 fabric in a low-loss resin, 2.52 ps/in, against 13.8 ps/in for the traditional weave of the same style ^[6]. The worst case is a statistical tail: as Simonovich puts it, a design over the length does not have to fail, but if you build enough boards, some will degrade ^[1].

Worked example: a 60 mm PCIe Gen 4 pair

A 60 mm (2.4 in) stripline pair at 16 GT/s, routed straight along the board edge, so parallel to the weave:

• Traditional weave, worst case: 60 × 0.628 = 37.7 ps of skew, 0.60 UI at 62.5 ps. The null sits at 1 / (2 × 37.7 ps) = 13.3 GHz, 1.7 times the 8 GHz Nyquist frequency. Most boards will be far better than this (the mean is a quarter of the tail), but a fraction of a production run will not.
• Spread glass, worst case: 60 × 0.099 = 6.0 ps, 0.095 UI, with the null near 84 GHz, out of the band that matters.
• The routing rule: the PCIe CEM intra-pair limit of 5 mil on an add-in card ^[1] is 0.127 mm, which at 6–7 ps/mm is under 1 ps. Matching the lengths to 5 mil does nothing about 38 ps of weave skew, and since the weave skew depends on where the traces happen to fall on the glass ^[1], you cannot predict it at layout time and tune it out.

Check the skew and length rules for PCIe and other interfaces →

Choosing the glass

The weave pitch is the spacing of the yarns, 25.4 mm divided by the count per inch. These are the counts from Isola’s style table ^[7]:

A pitch of about 0.4 mm is the same order as the spacing of a differential pair, which is why the position of a pair on the weave matters. Isola calls a fabric with balanced counts a square weave, and spread glass a fabric whose yarns have been spread out; its photographs of 106 show the open windows between yarns narrowing when the glass is spread, and it describes spread glass in both directions as the current industry standard ^[7].

What the published data says about the choice:

• Spread against traditional weave of the same style: 2.52 against 13.8 ps/in predicted worst case for 1080 in a low-loss resin, and a measured range of laminate Dk across trace positions of 0.14 against 0.50 ^[6]. This is the largest single improvement in the data.
• Style substitutions: for Isola FR408HR, the I-Connect007 article suggests 1086 in place of 1080, 1067 in place of 106, and two plies of 3313 in place of one 7628 ^[3]. Each swaps an open or unbalanced weave for a tighter, square one of similar thickness.
• Style still matters within a model: Manukovsky, Shlepnev and Mordooch simulated 4 mil traces 4 mil apart over a 4 mil laminate (glass Dk 6, resin 3.5) for four styles. With the pair at a random position, the skew exceeded 3 ps/in in about 44 % of cases for 1078, 66 % for 1080 and 76 % for 3313, and only 1035 stayed under that limit ^[5]. They also note that wider traces average the dielectric and see less variation, so the result depends on the trace geometry ^[5].
• Resin and glass Dk: the bigger the difference between them, the bigger the skew. With a traditional weave, the FR-4 resin in Dudek’s study gave less skew than the low-loss resin (9.71 against 13.8 ps/in predicted), because its Dk is closer to that of the glass ^[6]. Low-loss materials therefore need the glass choice more, not less.

Routing at an angle

If a pair runs at an angle to the weave, each trace crosses yarns and gaps in turn and both see the same average Dk. TI describes two ways ^[4]:

• Rotate the image. The whole signal layer is rotated 10° to 35° relative to the weave. The fabricator can do this without any change to your layout data.
• Zig-zag routing. The pair is routed in a zig-zag across the board instead of straight along x or y.

Intel’s paper proposed 10° for long traces, or a 10° panel rotation ^{[2, 3]}. Both work, but the I-Connect007 article calls them a hassle to implement and expensive ^[3]. A rotated image generally fits fewer boards on a production panel, so ask the fabricator before relying on it.

The angle needed is small because of the pitch. A trace at angle θ moves sideways by one weave pitch every p / tan θ along its length. For a 0.423 mm pitch (1080 warp, 1086, 2116) that is every 2.4 mm at 10° and every 1.6 mm at 15°, so a 60 mm pair crosses about 25 and 38 yarns and averages them out. For the 0.819 mm fill pitch of 7628 it is every 4.6 mm at 10°. This is geometry, not a measured result: it shows why a few degrees are enough on a long run and why short straight segments are not the concern.

A checklist

1. Work out the skew budget for each fast interface. At 8 GT/s and above, assume weave skew can use most of it on long straight pairs.
2. Specify spread glass for the layers under fast pairs and ask the fabricator which glass styles its stackup uses; prefer square weaves such as 1035, 1067, 1078, 1086 and 3313 over 106, 1080 and 7628.
3. Keep long pairs off the 0° and 90° axes where the layout allows, or ask the fabricator to rotate the image of those layers by 10° or more.
4. Match lengths to the interface rule, but do not count on length tuning to remove weave skew.
5. For PCIe Gen 4 and Gen 5, low-loss laminates, and pairs longer than a few centimetres, simulate the channel with Dk_min and Dk_max as Simonovich describes ^[1].

Build the stackup ply by ply and note the glass style of each layer →

Size the pair in the impedance calculator →

Tools used in this guide

• Propagation Delay, εeff & Timing – Propagation delay, length matching from skew, rise time to bandwidth, critical length and wavelength.
• Interface Design Rules – Impedance, skew, loss budget and length limits of PCIe, USB, Ethernet, HDMI, DDR and other interfaces, applied to a layer of your own stackup with the field solver.
• Layer Stack Manager – 178 rigid fab stackups plus six flex and rigid-flex design starters, with linked regions, editable materials and per-layer impedance.
• Impedance Calculator – Single-ended and differential microstrip, coated and embedded microstrip, stripline, coplanar lines and broadside differential pairs, solved with a 2D field solver.

Sources

1. L. Simonovich, Practical Fiber Weave Effect Modeling, white paper, issue 2, LAMSIM Enterprises, 10 January 2011: Equation 1 (delay from Dk), the summary of Intel’s measurements (p. 5), Figure 4 and 5 (106 and 7628 Dk), Equation 6 (skew resonance), the PCIe CEM Rev. 2.0 budget (p. 12) and the conclusions (p. 23).
2. J. Loyer, R. Kunze, X. Ye, “Fiber Weave Effect: Practical Impact Analysis and Mitigation Strategies,” DesignCon 2007. Not publicly available; its measured statistics and mitigations are quoted here as summarised in sources 1 and 3.
3. B. Simonovich, “Bert’s Practical Design Notes: Fiber Weave-Induced Timing Skew,” I-Connect007 Design007, 17 September 2011: 10° routing and panel rotation, Isola FR408HR style substitutions, PCIe Gen2 eye closure against length.
4. Texas Instruments SNLA426, High-Speed PCB Layout for PCIe Gen 5 (June 2023), §8 PCB Grain and Fiber Weave Selection, Figures 8-1 and 8-2.
5. A. Manukovsky (Intel), Y. Shlepnev (Simberian), S. Mordooch, “Evaluation of Delay Uncertainty in PCB Interconnects Due to Fiber Weave Effect,” arXiv:2210.05779, October 2022: Table 1, Sections II and V, Figure 14.
6. R. Dudek, J. Kuhn, P. Goldman, “Opening Eyes on Fiber Weave and CAF,” IPC technical paper, 2009: traditional against spread 1080 fabric, finite-element and HyperLynx skew.
7. Isola, Glass Fabric (April 2022): p. 2 style table (warp and fill counts), p. 3 definitions of spread glass and square weave, p. 5 standard and spread 106.

Related guides

• PCB Prepreg Glass Styles: 106, 1080, 2116, 3313 and 7628 Compared
• PCIe PCB Routing Guidelines: Impedance, Return Paths, Vias, Loss and Skew
• Via Stub Resonance: How Long a Stub Can Be, and When to Back-Drill

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