HDMI PCB Layout Guidelines
Route HDMI TMDS pairs at 100 Ω differential (±15 %), match each pair within 5 mil on a source board, use no AC-coupling capacitors on a plain link, and keep copper out from under the connector pads.
Every rule below comes from a chip vendor’s layout guide or data sheet, each named in the sources; none is quoted from the HDMI specification itself. Vendor guides differ, so treat their numbers as good practice and follow your own device’s guide where it is stricter.
Key numbers
| Quantity | HDMI 1.4 (TMDS, 3.4 Gb/s) | HDMI 2.0 (TMDS, 6 Gb/s) |
|---|---|---|
| Line rate | 3.4 Gb/s | 6 Gb/s |
| Nyquist frequency | 1.7 GHz | 3 GHz |
| Encoding | TMDS, 8b/10b, clock forwarded on its own pair | TMDS, 8b/10b, clock at 1/40 of the data rate above 3.4 Gb/s |
| Impedance | 100 Ω differential (85–115 Ω) | 100 Ω differential (85–115 Ω) |
| Second impedance | 50 Ω from each line to ground | 50 Ω from each line to ground |
| Intra-pair skew (source board) | 0.127 mm (5 mil) | 0.127 mm (5 mil) |
| Channel-to-channel skew (source board) | 25.4 mm (1 in) | 25.4 mm (1 in) |
| Laminate the lengths assume | ≤ 0.17 dB per inch per GHz | ≤ 0.17 dB per inch per GHz |
- HDMI 1.4 (TMDS, 3.4 Gb/s): 100 Ω ±15 % differential; TI allows 75–110 Ω between a GPU and a redriver on a source board.
HDMI 1.4 (TMDS, 3.4 Gb/s) routing rules
Three TMDS data pairs and a clock pair, up to 340 MHz clock.
| Rule | Requirement | Basis |
|---|---|---|
| Impedance | 100 Ω ±15 % differential, 50 Ω ±15 % single-ended. | Vendor guide [1] |
| Intra-pair skew | 0.15 of a bit time. On a source board that is 5 mil of trace; on a sink board TI asks for 2 mil. The receive side of the link gets a wider electrical budget (0.4 of a bit time) but a tighter routing rule, because the redriver has already spent part of it. | Vendor guide [2] |
| Channel-to-channel skew | 0.2 of a character time — 1 in of trace on a source board, but only 0.10 in on a sink board. All three data pairs and the clock must land on the same pixel, so unlike PCIe or USB this really is a hard matching requirement. | Vendor guide [2] |
| Trace loss | Published length limits assume 0.1–0.17 dB per inch per GHz. A lossier board must be routed shorter. TI allows 1–16 in from the source to a redriver at 6 Gb/s, and 0.75–2 in from the redriver to the receptacle. | Vendor guide [2] |
| AC coupling | None: TMDS is DC-coupled, because the sink biases the pair through its 50 Ω pull-ups. A redriver in AC-coupled transmit mode needs 85–253 nF and a 499 Ω pull-down to ground on every output between the capacitor and the receptacle, or the common mode is out of spec. | Vendor guide [2] |
| Termination | On-die: 50 Ω to the 3.3 V termination supply at the sink, driven by a 10 mA current sink, so nothing external belongs on the pair. | Vendor guide [4] |
| Spacing | 5W between pairs, and 8W to 10W around the clock pair; at least 30 mil to any other signal, 50 mil to a periodic one. | Vendor guide [2] |
| Vias | At most two vias from the source to a redriver and one from a redriver to the receptacle, equal counts on both traces, stubs under 15 mil. | Vendor guide [2] |
| Reference plane | Solid ground under the whole run, no plane splits, stitching vias within 200 mil of any layer change. | Vendor guide [1] |
| Connector pads | No metal layer or trace under or between the pads of the HDMI connector. Copper left there drags the differential impedance below 75 Ω and fails the board in TDR testing — the classic HDMI layout mistake. | Vendor guide [3] |
| ESD protection | Within 0.5 in of the receptacle, with any series resistor to the redriver under 2.5 Ω and within 0.25 in of the protector. | Vendor guide [2] |
| Polarity | Swapping the two lines of a pair is not allowed, so a P/N mix-up has to be fixed in the schematic. | Vendor guide [1] |
Check HDMI 1.4 (TMDS, 3.4 Gb/s) on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
HDMI 2.0 (TMDS, 6 Gb/s) routing rules
The same four pairs at 6 Gb/s, with the clock running at a fortieth of the data rate.
| Rule | Requirement | Basis |
|---|---|---|
| Impedance | 100 Ω ±15 % differential, 50 Ω ±15 % single-ended. | Vendor guide [1] |
| Intra-pair skew | 0.15 of a bit time, which is about 25 ps at 6 Gb/s: 5 mil on a source board, 2 mil on a sink board. | Vendor guide [5] |
| Channel-to-channel skew | 0.2 of a character time, about 333 ps at 6 Gb/s: 1 in on a source board, 0.10 in on a sink board. | Vendor guide [5] |
| Trace loss | 0.1–0.17 dB per inch per GHz for the published lengths to hold, with crosstalk between neighbouring pairs below −24 dB up to 3 GHz. | Vendor guide [5] |
| AC coupling | None on a plain HDMI link. A redriver used in AC-coupled mode needs 85–253 nF within 0.3 in of the device, plus the 499 Ω pull-downs. | Vendor guide [5] |
| Termination | On-die 50 Ω to the termination supply; nothing external. | Vendor guide [4] |
| Spacing | 5W between pairs, 8W–10W around the clock pair, 30 mil to other signals, 50 mil to periodic ones. | Vendor guide [5] |
| Vias | One or two vias per segment, matched on both traces, stubs under 15 mil, no unconnected via pads. | Vendor guide [1] |
| Connector pads | Keep copper out from under and between the connector pads, or the launch falls below 75 Ω. | Vendor guide [3] |
| Test points | None on a high-speed pair, and no stubs of any kind. | Vendor guide [1] |
Check HDMI 2.0 (TMDS, 6 Gb/s) on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
Related guides
- AC Coupling Capacitors on High-Speed Links: the Value for Every Interface
- Controlled Impedance Explained: Microstrip, Stripline and Solder Mask
- PCB Crosstalk and the 3W Rule: How Much Spacing Is Enough?
Sources
- TI SLLA414A — High-Speed Layout Guidelines for Signal Conditioners and USB Hubs (rev. January 2026). §2.3 HDMI: 340 MHz clock and 1.7 GHz Nyquist at HDMI 1.4b, 3 GHz at 2.0b, 100 Ω ±15 % / 50 Ω ±15 %, intra-pair 0.15 of a bit time, inter-pair 0.2 of a character time, no AC capacitors, no polarity reversal; §3–§4 the plane, stitching, via, spacing and capacitor rules.
- TI TMDS1204 data sheet SLLSF57A (Tables 8-2 and 8-6, §8.5.1). Source and sink routing budgets: 5 mil and 2 mil intra-pair, 1 in and 0.10 in channel-to-channel, via counts, 0.1–0.17 dB/in/GHz trace loss, 85–253 nF coupling with the 499 Ω pull-down, ESD placement, 8W–10W around the clock pair.
- TI HDMI Design Guide (June 2007). 100 Ω ±15 %, intra-pair 0.15 of a bit time at the source and 0.4 at the sink, inter-pair 0.2 of a character time, and the warning that copper under the connector pads drops the impedance below 75 Ω and fails TDR.
- TI TMDS141 data sheet SLLS737D. Integrated 50 Ω terminations to the 3.3 V termination supply at every receiver input, 10 mA current-mode driver, and the resulting output levels — the evidence that TMDS needs no external termination.
- TI TDP0604 data sheet SLLSFJ8A (Table 9-2) and TMDS1204 SLLSF57A. 6 Gb/s HDMI 2.0 budgets: 1–16 in source to device and 0.75–2 in device to receptacle, 0.1–0.2 dB/in/GHz, 5 mil intra-pair and 1 in channel-to-channel on a source board, −24 dB crosstalk, coupling capacitors of 85–253 nF.
Layout guidelines for other interfaces
DisplayPort · USB 3.2 · USB 2.0 · DDR4 · LPDDR4 · RGMII · RMII · SGMII · 1000BASE-T Ethernet · MIPI D-PHY · SATA · PCIe