MIPI D-PHY PCB Layout Guidelines
Route MIPI D-PHY lanes to 100 Ω differential and 50 Ω single-ended at the same time (couple the pair loosely), keep intra-pair skew to about 8 ps and data-to-clock skew to 40 ps at 2.5 Gb/s, and add no series capacitors: D-PHY is DC-coupled.
Every rule below comes from a chip vendor’s layout guide or data sheet, each named in the sources; none is quoted from the MIPI D-PHY specification itself. Vendor guides differ, so treat their numbers as good practice and follow your own device’s guide where it is stricter.
Key numbers
| Quantity | MIPI D-PHY (CSI-2 / DSI) |
|---|---|
| Line rate | 2.5 Gb/s |
| Nyquist frequency | 1.25 GHz |
| Encoding | Double data rate: the clock lane runs at half the data rate, with a single-ended 1.2 V low-power mode on the same wires |
| Impedance | 100 Ω differential (85–115 Ω) |
| Second impedance | 50 Ω from each line to ground (low-power mode) |
| Intra-pair skew | 8 ps |
| Data lane to clock lane skew | 40 ps |
| Longest route | 254 mm (10 in) |
- TI allows ±15 %, Efinix and Renesas ±10 % to ±20 %. The single-ended value matters just as much, because low-power mode drives each wire on its own.
Routing rules
Camera and display lanes: a differential high-speed mode and a single-ended low-power mode on the same pair.
| Rule | Requirement | Basis |
|---|---|---|
| Coupling | Couple the pair loosely: it has to meet 100 Ω differential and 50 Ω single-ended at the same time. A tightly coupled pair optimised only for 100 Ω differential gets the single-ended impedance wrong, and the two wires disturb each other during the single-ended low-power transitions. This is the mistake that breaks D-PHY links that look fine on a differential TDR. | Vendor guide [1] |
| Impedance | 100 Ω differential and 50 Ω single-ended. | Vendor guide [1] |
| Intra-pair skew | About one fiftieth of a unit interval, roughly 8 ps at 2.5 Gb/s. Vendors route it as 5 mil, or under 1 ps where the guide is strict. The specification states it as mode-conversion S-parameters rather than a length, so the picosecond figure is an estimate the vendor offers. | Vendor guide [1] |
| Data to clock skew | 0.1 of a unit interval, 40 ps at 2.5 Gb/s. | Vendor guide [1] |
| AC coupling | None. D-PHY is DC-coupled, and series capacitors would destroy both the high-speed common mode and low-power mode. For the same reason, no in-line ESD diodes, common-mode chokes or extra components on the lanes. | Vendor guide [4] |
| Termination | On-die, about 100 Ω differential, switched on only for high-speed mode; low-power mode sees a high-impedance receiver. Nothing external. | Vendor guide [2] |
| Trace length | Up to 10 in per TI, or 200 mm from a module connector per Toradex. | Vendor guide [1] |
| Vias and stubs | At most two vias per trace, no stubs and no test points, equal via counts across all lanes. | Vendor guide [1] |
| Reference plane | Solid ground under the whole run and never across a plane split; ground vias placed symmetrically beside any signal via. | Vendor guide [2] |
| Spacing | Five trace widths between pairs, twice the pair’s own spacing to any other trace, 50 mil to a clock, and bends of at least 135°. | Vendor guide [2] |
| Clock lane | The clock lane runs at half the data rate, because the data is clocked on both edges. Sizing the clock trace for the full data rate is a common slip. | Vendor guide [3] |
| Levels | Low-power mode swings 0 to 1.2 V single-ended; high-speed mode is 200 mV differential around a 200 mV common mode. | Vendor guide [3] |
Check MIPI D-PHY (CSI-2 / DSI) on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
Related guides
- Controlled Impedance Explained: Microstrip, Stripline and Solder Mask
- PCB Crosstalk and the 3W Rule: How Much Spacing Is Enough?
Sources
- TI SPRACP4A — Jacinto 7 High-Speed Interface Design Guidelines (rev. June 2024). Table 3-12 for CSI-2 and DSI: 85/100/115 Ω differential with 50 Ω single-ended, intra-pair skew estimated at one fiftieth of a unit interval, 40 ps data-to-clock skew (0.1 UI), 10 in maximum length, two vias and no stubs, and the note that the pairs must be loosely coupled because of the single-ended low-power mode.
- TI DS90UB936-Q1 data sheet SNLS571C (§10.1.3) and Efinix UG-PCB-MIPI v1.0. 100 Ω ±10 % coupled routing, 5 mil intra-pair matching, no routing over plane splits, at most two vias per trace, pair separation of five trace widths, bends of 135° or more, and stitching capacitors of 1 µF or less if a split must be crossed.
- NXP AN13573 — MIPI D-PHY electrical characteristics (Rev. 1.1, August 2024). Table 2: low-power output 1.1–1.3 V, high-speed common mode 150–250 mV and differential swing 140–270 mV; §2.4 the double-data-rate clocking that puts the clock lane at half the data rate.
- MIPI Alliance — D-PHY specification page. The specification itself is available to members only, so every value here comes from a chip-vendor guide restating it. Version 3.0 raised the rate to 9 Gb/s per lane; 2.5 Gb/s is the common v1.2 ceiling used above.
Layout guidelines for other interfaces
HDMI · DisplayPort · USB 3.2 · USB 2.0 · DDR4 · LPDDR4 · RGMII · RMII · SGMII · 1000BASE-T Ethernet · SATA · PCIe