DisplayPort PCB Layout Guidelines
Route DisplayPort main-link pairs at 100 Ω differential (±10 %), keep intra-pair skew within 20 ps (about 5 mil), AC-couple every lane with 75–200 nF, and do not match lanes to each other: link training deskews them.
Every rule below names the document it comes from: the DisplayPort specification where it makes the rule mandatory, otherwise a chip vendor’s layout guide. Vendor guides differ, so treat their numbers as good practice and follow your own device’s guide where it is stricter.
Key numbers
| Quantity | DisplayPort 1.2 (HBR2, 5.4 Gb/s) | DisplayPort 1.4 (HBR3, 8.1 Gb/s) |
|---|---|---|
| Line rate | 5.4 Gb/s | 8.1 Gb/s |
| Nyquist frequency | 2.7 GHz | 4.05 GHz |
| Encoding | 8b/10b, 1.62 / 2.7 / 5.4 Gb/s link rates | 8b/10b (128b/132b only arrives with DisplayPort 2.0 UHBR) |
| Impedance | 100 Ω differential (90–110 Ω) | 100 Ω differential (90–110 Ω) |
| Second impedance | 50 Ω from each line to ground | 50 Ω from each line to ground |
| Intra-pair skew | 20 ps | 20 ps |
- DisplayPort 1.2 (HBR2, 5.4 Gb/s): TI asks for ±10 %, NXP for ±20 %; some platforms deliberately target 85 Ω instead, to cut loss and match the connector.
DisplayPort 1.2 (HBR2, 5.4 Gb/s) routing rules
Up to four AC-coupled main-link lanes, each trained and deskewed on its own.
| Rule | Requirement | Basis |
|---|---|---|
| Impedance | 100 Ω differential ±10 %, 50 Ω single-ended ±15 %. The AUX channel is also routed as a 100 Ω pair. | Vendor guide [1] |
| Intra-pair skew | 20 ps in the specification, which vendors turn into about 5 mil of trace (2 mil on some redrivers). | Vendor guide [1] |
| Lane-to-lane skew | No requirement: the link deskews each lane during training, so lanes do not have to match. | Vendor guide [1] |
| AC coupling | Required on the main link: 75–200 nF, 100 nF typical, same value and package on both lines of a pair, 0402 preferred and 0603 the largest allowed. | Specification [2] |
| Termination | On-die, 100 Ω differential at both ends; the link is doubly terminated and AC-coupled. | Vendor guide [2] |
| Trace loss | Around 0.35–0.5 dB per inch on FR-4, plus about 0.25 dB for each via pair, so vias — not trace length — often set the reach. | Vendor guide [2] |
| Vias | Two or fewer per trace, pad 25 mil or less and finished hole 14 mil or less, placed as a symmetric pair, with one to three ground stitching vias per pair. | Vendor guide [2] |
| Reference plane | Never straddle a plane split; keep the same ground reference through the whole run. | Vendor guide [2] |
| Spacing | At least four times the dielectric height to other pairs, 30 mil to noisy or faster-edged signals, and bends of 135° or more. | Vendor guide [2] |
| Length matching | Correct a mismatch in the segment where it happens, and keep serpentine jogs at least three trace widths long. | Vendor guide [2] |
| Connector pads | No copper under or between the connector pads; large pads and vias pull the impedance down. | Vendor guide [3] |
Check DisplayPort 1.2 (HBR2, 5.4 Gb/s) on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
DisplayPort 1.4 (HBR3, 8.1 Gb/s) routing rules
The same four lanes at 8.1 Gb/s, where laminate and vias start to decide the reach.
| Rule | Requirement | Basis |
|---|---|---|
| Impedance | 100 Ω differential ±10 %, 50 Ω single-ended ±15 %. | Vendor guide [1] |
| Intra-pair skew | 20 ps, about 5 mil of trace; tighten to 2 mil where the redriver asks for it. | Vendor guide [1] |
| Lane-to-lane skew | Not required — each lane is deskewed during link training. | Vendor guide [1] |
| AC coupling | Required on every main-link lane: 75–200 nF (some parts allow up to 265 nF), identical parts placed symmetrically, 0402 preferred. | Specification [2] |
| Termination | On-die 100 Ω at both ends; some receivers can be reprogrammed to 80 Ω to match a lower board impedance. | Vendor guide [1] |
| Trace loss | At 4.05 GHz plain FR-4 costs roughly 0.7 dB per inch, so a long run needs a better laminate or a redriver. | Vendor guide [2] |
| Fibre weave | Route long runs at an angle to the glass weave, or use a spread-glass laminate: weave skew is a real effect at 4 GHz. | Vendor guide [2] |
| Vias | Two or fewer per trace, symmetric pairs, stubs under 15 mil or back-drilled, anti-pads of about 30 mil on every layer with no unconnected pads. | Vendor guide [1] |
| Reference plane | One ground reference from end to end, stitching vias within 200 mil of a layer change, stitching capacitors of 1 µF or less if a split must be crossed. | Vendor guide [1] |
| Spacing | 5W between pairs, 30 mil keep-out to other signals, 50 mil to clocks, bends of at least 135°, package escape within 0.25 in. | Vendor guide [1] |
Check DisplayPort 1.4 (HBR3, 8.1 Gb/s) on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
Related guides
- AC Coupling Capacitors on High-Speed Links: the Value for Every Interface
- Controlled Impedance Explained: Microstrip, Stripline and Solder Mask
- Reading S4P Files: Differential Loss, Return Loss and Mode Conversion
Sources
- TI SLLA414A — High-Speed Layout Guidelines for Signal Conditioners and USB Hubs (rev. January 2026). §2.4 DisplayPort: 5.4 Gb/s with a 2.7 GHz Nyquist frequency at HBR2 and 8.1 Gb/s with 4.05 GHz at HBR3, 100 Ω ±10 % / 50 Ω ±15 %, 20 ps intra-pair (about 5 mil), AC capacitors required, no inter-pair requirement.
- NXP AN10798 — DisplayPort PCB layout guidelines (Rev. 01, March 2009). 50 Ω ±15 % single-ended and 100 Ω ±20 % differential, 5 mil intra-pair, coupling capacitors of 75–200 nF (100 nF best, 0402 preferred), via geometry and 0.25 dB per via pair, 0.35–0.5 dB per inch of FR-4, bend and serpentine geometry, and Intel’s move to 85 Ω on some platforms.
- TI DisplayPort Design Guide (April 2009). 100 Ω ±10 %, 20 ps intra-pair skew and 2 UI between lanes, and the rule that no metal may sit under or between the connector pads.
Layout guidelines for other interfaces
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