1000BASE-T Ethernet PCB Layout Guidelines
Route the four 1000BASE-T MDI pairs at 100 Ω differential (±10 %), match the two traces of each pair within 20 mil, keep each under 2 in, leave the pairs unmatched to each other, and keep metal out from under the magnetics.
Every rule below names the document it comes from: the 1000BASE-T Ethernet specification where it makes the rule mandatory, otherwise a chip vendor’s layout guide. Vendor guides differ, so treat their numbers as good practice and follow your own device’s guide where it is stricter.
Key numbers
| Quantity | 1000BASE-T (MDI) |
|---|---|
| Line rate | 0.25 Gb/s |
| Nyquist frequency | 0.0625 GHz |
| Encoding | PAM-5, 125 MBd per pair, four pairs |
| Impedance | 100 Ω differential (90–110 Ω) |
| Second impedance | 50 Ω from each line to ground |
| Pair length matching (P vs N) | 0.508 mm (20 mil) |
| Longest route | 50.8 mm (2 in) |
Routing rules
The four twisted pairs between a gigabit PHY and its magnetics and RJ45.
| Rule | Requirement | Basis |
|---|---|---|
| Signalling | 125 MBd per pair, PAM-5 (2 bits per symbol) on four pairs, so 250 Mb/s per pair and 1 Gb/s in total. | Specification [5] |
| Impedance | 100 Ω differential ±10 %, and 50 Ω from each line to ground. Match the impedance to the cable the board drives; a mismatch costs throughput and can break the link. | Vendor guide [1] |
| Pair matching | 20 mil between the two traces of a pair at 1 Gb/s, 50 mil at 10/100 Mb/s. Given as a length, not a time. Put the compensation at the end where the mismatch is. | Vendor guide [1] |
| Pair-to-pair matching | Not required: the PHY measures and corrects the delay between the four pairs, as IEEE 802.3 Clause 40 demands of it. | Vendor guide [3] |
| Trace length | Under 2 in (2000 mil) per MDI trace. | Vendor guide [1] |
| AC coupling | None in series: the transformer isolates the link. Each PHY-side centre tap gets its own 0.1 µF to ground. Never tie the four centre taps together — the common-mode voltage of a voltage-mode driver differs from pair to pair and with the speed mode. | Vendor guide [3] |
| Under the magnetics | No metal on any layer under the magnetics; metal under an RJ45 with integrated magnetics is allowed. The transformer couples noise into anything beneath it. Void the planes about 20 mil beyond the body, on at least two layers. | Vendor guide [1] |
| Chassis ground | Isolate earth ground from the board with a keep-out of at least 20 mil on every layer. Bridge the moat only with a capacitor and a resistor of 1 MΩ or more; vendors use 1 nF / 2 kV in 1206 parts either side of the connector. | Vendor guide [1] |
| Termination | On-die in modern PHYs. On the cable side, Bob Smith termination: 4 × 75 Ω commoned through 1000 pF / 2 kV to chassis ground. | Vendor guide [3] |
| Spacing | 3W minimum from copper pour on the same layer, 5W preferred; at least 30 mil to any other pair. | Vendor guide [1] |
| Vias and stubs | Route a whole pair on one layer: no crossovers, no vias and no stubs on the MDI traces. Put a ground via beside any signal via you cannot avoid. | Vendor guide [2] |
| Magnetics | HIPOT at least 1500 V rms, 1 CT : 1 CT turns ratio, open-circuit inductance at least 350 µH, insertion loss at most 1 dB to 100 MHz. | Vendor guide [3] |
| ESD protection | Protection diodes belong on the PHY side of the magnetics, not on the connector side. The cable side swings far in common mode during normal operation, which destroys protectors placed there. | Vendor guide [1] |
Check 1000BASE-T (MDI) on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
Related guides
- Controlled Impedance Explained: Microstrip, Stripline and Solder Mask
- PCB Crosstalk and the 3W Rule: How Much Spacing Is Enough?
Sources
- TI SNLA387 — Ethernet PHY PCB Design Layout Checklist (June 2021). MDI and MII trace rules: 100 Ω ±10 % / 50 Ω to ground, 20 mil pair matching at 1 Gb/s, 2 in MDI and 6 in MII length limits, 3W/5W keep-out, 20 mil earth-ground moat, magnetics keep-out, ESD diode placement.
- TI DP83867IR/CR data sheet SNLS484 (layout in §9.2.2.1.1 of revision J, 2026; §9.2 and §9.4 in earlier revisions). MDI 50 Ω to ground and 100 Ω differential, 0.1 µF per isolated centre tap, no metal under the transformer, RGMII 11 ps (60 mil) intra-group skew, internal RGMII delay in 0.25 ns steps.
- Microchip KSZ9031RNX data sheet DS00002117 (§3.9.3, §12.0). Separate 0.1 µF common-mode capacitors per centre tap, Bob Smith termination 4 × 75 Ω with 1000 pF/2 kV, magnetics HIPOT 1500 V rms and 350 µH OCL, RGMII pad-skew registers in 0.06 ns steps, inter-pair delay correction in the PHY.
- Microchip ENT-AN1231 VSC8541 Design and Layout Guide, VPPD-04420 Rev 1.1. MAC-interface series termination R = 50 Ω − driver output impedance (27–39 Ω on this PHY), 120 mil matching per port, external 1.5–2.0 ns RGMII clock “trombone” delay, Bob Smith on the cable-side centre taps.
- IEEE P802.3ab draft, Clause 40 (1.4.183 symbol rate). Defines the 1000BASE-T symbol rate as 125 MBd. The published IEEE 802.3 standard is not free; the PAM-5 / four-pair arithmetic is confirmed by the UNH-IOL tutorial on 1000BASE-T PMA.
Layout guidelines for other interfaces
HDMI · DisplayPort · USB 3.2 · USB 2.0 · DDR4 · LPDDR4 · RGMII · RMII · SGMII · MIPI D-PHY · SATA · PCIe