DDR4 PCB Layout Guidelines
Route DDR4 at 40 Ω single-ended (80 Ω differential for CK and DQS), use fly-by topology for clock, address and command, match DQ to DQS inside each byte lane (2 ps per TI), and do not match byte lanes to each other.
Every rule below names the document it comes from: the DDR4 specification where it makes the rule mandatory, otherwise a chip vendor’s layout guide. Vendor guides differ, so treat their numbers as good practice and follow your own device’s guide where it is stricter.
Key numbers
| Quantity | DDR4 (up to 3200 MT/s) |
|---|---|
| Line rate | 3.2 Gb/s |
| Nyquist frequency | 1.6 GHz |
| Encoding | Single-ended pseudo-open-drain (POD), double data rate |
| Impedance | 40 Ω single-ended (36–44 Ω) |
| Second impedance | CK and DQS pairs (differential) |
| CK and DQS intra-pair skew | 0.4 ps |
| DQ to DQS inside a byte lane | 2 ps |
| Longest route (delay) | 500 ps |
- TI and Efinix use 40 Ω, AMD 39 Ω on the main board and 50 Ω in the BGA breakout, NXP offers 40 Ω or 50 Ω.
Routing rules
Single-ended data and address lines with differential clock and strobes, routed fly-by.
| Rule | Requirement | Basis |
|---|---|---|
| Impedance | 40 Ω single-ended ±10 %, and 80 Ω differential for CK and DQS. Differential is simply twice the single-ended value: set the pair pitch to about 2W rather than chasing a spacing number. Where a guide says 50 Ω single-ended, it pairs it with 100 Ω differential. | Vendor guide [1] |
| DQ to DQS | Within 2 ps inside a byte lane per TI; AMD allows ±10 ps and NXP ±5 mil above 1600 MT/s. The tolerance follows each PHY’s deskew capability, so use the number from the controller you are designing with. | Vendor guide [1] |
| Byte lane to byte lane | Not required. TI states that matching lengths across byte lanes is neither required nor recommended. | Vendor guide [1] |
| CK to DQS | A deliberately wide, asymmetric window (AMD: −149 to +1796 ps), because write levelling absorbs it. The clock touches every device on the fly-by chain and is therefore slower than any one strobe. Over-tightening this fights the topology. | Vendor guide [2] |
| Address and command to CK | Within about 3 ps per segment at TI, ±8 ps (47 mil) at AMD, ±10 mil at NXP. | Vendor guide [1] |
| Route delay | Each byte lane and each address segment stays under 500 ps (TI); AMD allows 6 in of data route including the package. TI counts 1 ps as 5 mil of stripline, and asks you to divide microstrip lengths by 1.1 before adding them up, as JEDEC specifies. | Vendor guide [1] |
| Topology | Fly-by is mandatory for DDR4: clock, address and command run from the controller to each device in turn with a short stub at each one, and terminate at the end. T-branch routing is not supported. | Vendor guide [1] |
| Termination | VTT = half of VDDQ through a resistor equal to the trace impedance at the end of the fly-by chain, placed right after the last device. Series resistors at the driver are not allowed. A single-device design can drop VTT, but the differential clock still needs its terminator. | Vendor guide [1] |
| On-die termination | ODT is 240, 120, 80, 60, 48, 40 or 34 Ω, set from RZQ = 240 Ω ±1 %. The driver is 34 Ω or 48 Ω. | Specification [4] |
| Reference plane | No reference-plane cuts anywhere in the DDR routing area, and the plane directly adjacent to the signal layer. Watch out for the voids that via anti-pads create. Data and clock reference ground; address and command may reference the DDR supply if both ends of each route are bypassed. | Vendor guide [1] |
| Vias | At most two vias per data trace and three on clock, address and command, with the same via count on every net of a group. Return vias within 250 mil of the transition. | Vendor guide [1] |
| Spacing | 4W from a clock or strobe to anything else, 3W between address lines and between the bits of one byte; 2W is allowed for up to 500 mil near the ends. | Vendor guide [1] |
| Layer choice | Stripline is strongly preferred, and traces on adjacent layers must cross at right angles, offset by more than three times the trace-to-plane distance. | Vendor guide [1] |
| VREF | VREF for command and address is made on the board, routed on a 20 mil trace with 0.1 µF at each device, and must not share a plane with VTT. | Vendor guide [3] |
Check DDR4 (up to 3200 MT/s) on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
Related guides
- PCB Crosstalk and the 3W Rule: How Much Spacing Is Enough?
- Controlled Impedance Explained: Microstrip, Stripline and Solder Mask
Sources
- TI SPRAD06C — AM62x, AM62Lx DDR Board Design and Layout Guidelines (rev. March 2025). Tables 1-1, 2-6 and 2-7: 40 Ω / 80 Ω with ±10 %, 0.4 ps intra-pair, 2 ps DQ-to-DQS, 500 ps segment limits, 4W/3W spacing, zero plane cuts, via counts, fly-by requirement, VTT and VREF rules, and the 1 ps = 5 mil / ÷1.1 microstrip convention.
- AMD UG583 — UltraScale Architecture PCB Design User Guide. Main-board 39 Ω single-ended and 76 Ω differential with 50/86 Ω breakouts, ±10 ps data-to-strobe, 2 ps intra-pair, ±8 ps address-to-clock, and the −149 to +1796 ps clock-to-strobe window that write levelling allows.
- NXP AN5097 — Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces (Rev. 2, 2019). The 40 Ω and 50 Ω options with their matching differential values, ±5 mil intra-pair, ±20 mil (±5 mil above 1600 MT/s) data-to-strobe, VTT sizing and decoupling, and the rule that VREF and VTT may not share a plane.
- JEDEC JESD79-4 — DDR4 SDRAM. RZQ = 240 Ω ±1 %, the supported ODT values (240 down to 34 Ω) and the 34 Ω / 48 Ω driver settings. JEDEC does not specify PCB trace impedance at all; free registration is needed to download.
Layout guidelines for other interfaces
HDMI · DisplayPort · USB 3.2 · USB 2.0 · LPDDR4 · RGMII · RMII · SGMII · 1000BASE-T Ethernet · MIPI D-PHY · SATA · PCIe