RGMII PCB Layout Guidelines
RGMII needs more than 1.5 ns and less than 2.0 ns of extra clock delay, added either on the board or inside an RGMII-ID device. Route the lines at 50 Ω single-ended (a vendor rule), match each data group within 11 ps (about 60 mil) and keep runs under 6 in.
Every rule below names the document it comes from: the RGMII specification where it makes the rule mandatory, otherwise a chip vendor’s layout guide. Vendor guides differ, so treat their numbers as good practice and follow your own device’s guide where it is stricter.
Key numbers
| Quantity | RGMII (MAC ↔ PHY) |
|---|---|
| Line rate | 0.25 Gb/s |
| Nyquist frequency | 0.125 GHz |
| Encoding | DDR, 125 MHz clock (25 MHz at 100 Mb/s, 2.5 MHz at 10 Mb/s) |
| Impedance | 50 Ω single-ended (45–55 Ω) |
| Skew inside TXD[3:0] or RXD[3:0] | 11 ps |
| Longest route | 152 mm (6 in) |
- Single-ended. The RGMII specification itself sets no impedance; 50 Ω ±10 % is the vendor rule.
Routing rules
Reduced gigabit MII: four data lines per direction, clocked on both edges at 125 MHz.
| Rule | Requirement | Basis |
|---|---|---|
| Clock delay (before v2.0) | The board must add more than 1.5 ns and less than 2.0 ns of extra delay to the clock, relative to the data. Roughly 8–11 in of extra clock trace, which is why the “trombone” was replaced by internal delay. | Specification [1] |
| Clock delay (v2.0, RGMII-ID) | The delay may instead sit inside the device; such parts are called RGMII-ID. The MAC delays TXC, the PHY delays RXC. TI parts adjust it from 0 to 4 ns in 0.25 ns steps, Microchip in 0.06 ns steps. Mixing an RGMII-ID part with a board delay doubles it. | Specification [1] |
| Timing budget | Data-to-clock skew at the transmitter −500 to +500 ps; at the receiver 1.0 to 2.6 ns (1.8 ns typical). Setup and hold at least 1.2 ns each with integrated delay. | Specification [1] |
| Clock | Cycle 8 ns (7.2–8.8 ns), duty cycle 45–55 % at 1 Gb/s (40–60 % at 10/100 Mb/s), rise and fall at most 0.75 ns (20–80 %). | Specification [1] |
| Impedance | 50 Ω single-ended ±10 % (a vendor rule; the specification gives none). | Vendor guide [3] |
| Skew within a group | Under 11 ps between TXD[3:0], and between RXD[3:0]; TI calls that 60 mil on FR-4. Match transmit to transmit and receive to receive. The transmit group does not have to match the receive group. | Vendor guide [4] |
| Trace length | Under 2 in recommended, 6 in maximum. | Vendor guide [3] |
| Series termination | R = 50 Ω − the driver output impedance, placed at the driver. On a PHY with 11–23 Ω outputs that is 27–39 Ω; other parts integrate it. | Vendor guide [2] |
| Reference plane | An unbroken plane below (or above) every RGMII signal, with a ground via next to each signal via. | Vendor guide [2] |
| Spacing | 3W minimum from copper pour, 5W preferred; at least 30 mil to other signals. | Vendor guide [3] |
Check RGMII (MAC ↔ PHY) on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
Related guides
- Controlled Impedance Explained: Microstrip, Stripline and Solder Mask
- PCB Crosstalk and the 3W Rule: How Much Spacing Is Enough?
Sources
- RGMII specification v2.0 (Hewlett-Packard, 1 April 2002). Table 2 and its notes: the 1.5–2.0 ns board clock delay required before v2.0, the RGMII-ID internal delay added in v2.0, the setup/hold budget, clock cycle, duty cycle and edge rates. HSTL Class 1 signalling.
- Microchip ENT-AN1231 VSC8541 Design and Layout Guide, VPPD-04420 Rev 1.1. MAC-interface series termination R = 50 Ω − driver output impedance (27–39 Ω on this PHY), 120 mil matching per port, external 1.5–2.0 ns RGMII clock “trombone” delay, Bob Smith on the cable-side centre taps.
- TI SNLA387 — Ethernet PHY PCB Design Layout Checklist (June 2021). MDI and MII trace rules: 100 Ω ±10 % / 50 Ω to ground, 20 mil pair matching at 1 Gb/s, 2 in MDI and 6 in MII length limits, 3W/5W keep-out, 20 mil earth-ground moat, magnetics keep-out, ESD diode placement.
- TI DP83867IR/CR data sheet SNLS484 (layout in §9.2.2.1.1 of revision J, 2026; §9.2 and §9.4 in earlier revisions). MDI 50 Ω to ground and 100 Ω differential, 0.1 µF per isolated centre tap, no metal under the transformer, RGMII 11 ps (60 mil) intra-group skew, internal RGMII delay in 0.25 ns steps.
Layout guidelines for other interfaces
HDMI · DisplayPort · USB 3.2 · USB 2.0 · DDR4 · LPDDR4 · RMII · SGMII · 1000BASE-T Ethernet · MIPI D-PHY · SATA · PCIe