USB 2.0 PCB Layout Guidelines
Route the USB 2.0 D+/D− pair at 90 Ω differential (±15 %), match it within 50 mil, keep it under 4 in, and put no capacitors in series: High Speed is DC-coupled.
Every rule below names the document it comes from: the USB 2.0 specification where it makes the rule mandatory, otherwise a chip vendor’s layout guide. Vendor guides differ, so treat their numbers as good practice and follow your own device’s guide where it is stricter.
Key numbers
| Quantity | USB 2.0 High Speed |
|---|---|
| Line rate | 0.48 Gb/s |
| Nyquist frequency | 0.24 GHz |
| Encoding | NRZI with bit stuffing (the clock is carried in the data) |
| Impedance | 90 Ω differential (76.5–103.5 Ω) |
| Second impedance | 45 Ω from each line to ground |
| Intra-pair skew | 1.27 mm (50 mil) |
| Longest route | 102 mm (4 in) |
Routing rules
The D+/D− pair at 480 Mb/s, between the controller and its connector.
| Rule | Requirement | Basis |
|---|---|---|
| Impedance | The line between the receptacle and the series resistors must be 90 Ω ±15 % differential; each line is 45 Ω to ground. | Specification [1] |
| Intra-pair matching | 50 mil between D+ and D− on the board. Vendors differ widely here, from 2 mil to 150 mil. The specification itself only limits the cable, to 100 ps. | Vendor guide [2] |
| Trace length | Under 4 in, and the board may add at most 4 ns of delay on top of the 26 ns the cable is allowed. | Vendor guide [2] |
| AC coupling | None: High Speed is DC-coupled and series capacitors are not allowed. An edge-rate capacitor is permitted, but the total capacitance at the driver must stay under 75 pF and balanced within 10 %. | Specification [1] |
| Termination | On-die, 45 Ω from each line to ground at both ends. External series resistors, where used, sit within 200 mil of the controller. | Specification [1] |
| Pull-up | A High-Speed-capable device pulls D+ up through 1.5 kΩ ±5 % to 3.3 V; a downstream port pulls both lines down through 15 kΩ. | Specification [1] |
| Vias and stubs | At most four vias on the pair, no stub longer than 200 mil, and no test points. | Vendor guide [2] |
| Spacing | At least 30 mil to any other signal and 50 mil to a clock or other periodic signal. | Vendor guide [2] |
| Reference plane | Keep the pair over solid ground, never across a split or a void, and at least three dielectric heights from a plane edge. | Vendor guide [3] |
| Connector entry | Land the pair on the bottom layer for a through-hole receptacle, on the top layer for a surface-mount one. Entering from the far side turns the through-hole pin into a stub. | Vendor guide [2] |
| Edge rates | Rise and fall times are 4–20 ns and must match within 10 %. | Specification [1] |
Check USB 2.0 High Speed on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
Related guides
- Controlled Impedance Explained: Microstrip, Stripline and Solder Mask
- Is USB 3 85 Ω or 90 Ω? What the Specifications Actually Say
Sources
- Universal Serial Bus Specification Rev 2.0 (27 April 2000). §7.1.1.3 and §7.1.6.1: 90 Ω ±15 % board impedance, 45 Ω drivers, 75 pF edge-rate limit; §7.1.2 edge rates; §7.1.3 cable skew 100 ps; §7.1.5.2 pull-ups; Table 7-12 cable characteristics and the 26 ns cable delay.
- TI SPRAAR7J — High-Speed Interface Layout Guidelines (Feb 2023). Per-interface impedance, intra-pair skew and trace-length limits for TI SoCs (Appendix A), plus the general rules: 5W pair-to-pair spacing, 200 mil ground-via distance, < 15 mil via stubs, ≤ 0603 series parts.
- Silicon Labs AN0046 — USB Hardware Design Guidelines Rev 1.02. Skew budget (400 ps total, of which the cable takes 100 ps), plane-edge and plane-crossing rules, series resistors at the controller.
Layout guidelines for other interfaces
HDMI · DisplayPort · USB 3.2 · DDR4 · LPDDR4 · RGMII · RMII · SGMII · 1000BASE-T Ethernet · MIPI D-PHY · SATA · PCIe