SGMII PCB Layout Guidelines
Route SGMII at 100 Ω differential, keep intra-pair skew under 5 ps (about 30 mil), AC-couple every connection through 0.1 µF in an 0402 package or smaller, and do not match the transmit pair to the receive pair.
Every rule below names the document it comes from: the SGMII specification where it makes the rule mandatory, otherwise a chip vendor’s layout guide. Vendor guides differ, so treat their numbers as good practice and follow your own device’s guide where it is stricter.
Key numbers
| Quantity | SGMII (MAC ↔ PHY) |
|---|---|
| Line rate | 1.25 Gb/s |
| Nyquist frequency | 0.625 GHz |
| Encoding | 8b/10b, 1.25 GBd (1 Gb/s payload) |
| Impedance | 100 Ω differential (80–120 Ω) |
| Intra-pair skew | 5 ps |
| Longest route | 191 mm (7.5 in) |
- The receiver must present 80–120 Ω differential; boards are routed to 100 Ω.
Routing rules
Serial gigabit MII: one differential pair per direction at 1.25 GBd.
| Rule | Requirement | Basis |
|---|---|---|
| Signalling | 1.25 GBd, 8b/10b coded, so the clock content sits at 625 MHz. Differential output 150–400 mV. | Specification [1] |
| Impedance | 100 Ω differential; the receiver input is 80–120 Ω. | Vendor guide [2] |
| Intra-pair skew | Under 5 ps between the two traces of a pair, which TI calls 30 mil on FR-4. | Vendor guide [2] |
| Pair-to-pair | The transmit pair does not have to match the receive pair. In six-wire mode the receive pair must match the clock pair within 5 ps. | Vendor guide [2] |
| AC coupling | Every SGMII connection is AC-coupled through 0.1 µF, in an 0402 package or smaller. A larger body widens the pad and spoils the impedance at 625 MHz. An SFP cage usually has its own coupling capacitors, so do not add a second set. | Vendor guide [2] |
| Trace length | Up to 7500 mil on the TI SoCs that publish a limit. | Vendor guide [3] |
| Layer and reference | Route both traces of a pair on one layer, referenced to a parallel ground plane. | Vendor guide [2] |
| Termination | On-die; no external termination. | Vendor guide [2] |
| Spacing | At least 30 mil to other pairs, 5W to other signals. | Vendor guide [4] |
Check SGMII (MAC ↔ PHY) on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
Related guides
- AC Coupling Capacitors on High-Speed Links: the Value for Every Interface
- Controlled Impedance Explained: Microstrip, Stripline and Solder Mask
Sources
- Cisco Serial-GMII Specification ENG-46158 Rev 1.8 (2 Nov 2005). 1.25 GBd, 8b/10b, 625 MHz DDR clocking, LVDS-family levels per IEEE 1596.3, receiver input impedance 80–120 Ω, output swing 150–400 mV.
- TI DP83869HM data sheet SNLS614 (§9.4 layout). 100 Ω differential routing, 5 ps (30 mil) intra-pair skew, 0.1 µF 0402 coupling capacitors on every SGMII connection, six-wire clock matching, same-layer routing over a parallel ground plane, integrated termination.
- TI SPRAAR7J — High-Speed Interface Layout Guidelines (Feb 2023). Per-interface impedance, intra-pair skew and trace-length limits for TI SoCs (Appendix A), plus the general rules: 5W pair-to-pair spacing, 200 mil ground-via distance, < 15 mil via stubs, ≤ 0603 series parts.
- TI SNLA387 — Ethernet PHY PCB Design Layout Checklist (June 2021). MDI and MII trace rules: 100 Ω ±10 % / 50 Ω to ground, 20 mil pair matching at 1 Gb/s, 2 in MDI and 6 in MII length limits, 3W/5W keep-out, 20 mil earth-ground moat, magnetics keep-out, ESD diode placement.
Layout guidelines for other interfaces
HDMI · DisplayPort · USB 3.2 · USB 2.0 · DDR4 · LPDDR4 · RGMII · RMII · 1000BASE-T Ethernet · MIPI D-PHY · SATA · PCIe