LPDDR4 PCB Layout Guidelines
Route LPDDR4 and LPDDR4X at 40 Ω single-ended (80 Ω differential for CK and DQS), point to point with no board termination or VTT rail; keep each strobe shorter than its data lines, the clock longer than every strobe, and every route under 450 ps.
Every rule below comes from a chip vendor’s layout guide or data sheet, each named in the sources; none is quoted from the LPDDR4 specification itself. Vendor guides differ, so treat their numbers as good practice and follow your own device’s guide where it is stricter.
Key numbers
| Quantity | LPDDR4 / LPDDR4X (up to 4266 MT/s) |
|---|---|
| Line rate | 4.266 Gb/s |
| Nyquist frequency | 2.133 GHz |
| Encoding | Single-ended low-voltage swing terminated logic, double data rate |
| Impedance | 40 Ω single-ended (36–44 Ω) |
| Second impedance | CK and DQS pairs (differential) |
| DQS intra-pair skew | 1.5 ps |
| Longest route (delay) | 450 ps |
- TI and Efinix use 40 Ω; AMD uses 39 Ω (UltraScale) or 45 Ω (Versal).
Routing rules
Point-to-point low-power DDR: no board termination, per-bit deskew in the PHY.
| Rule | Requirement | Basis |
|---|---|---|
| Impedance | 40 Ω single-ended ±10 %, 80 Ω differential for CK and DQS. LPDDR4 and LPDDR4X are routed identically. | Vendor guide [1] |
| DQ to DQS | TI allows −49 to +2 ps: the strobe should be shorter than every data line in its byte. The window is asymmetric on purpose, so a length-matching tool set to match symmetrically will break it. AMD allows ±5 ps (UltraScale) or ±100 ps (Versal). | Vendor guide [1] |
| CK to DQS | The clock pair must be longer than every strobe pair, by 0 to 150 ps. | Vendor guide [1] |
| Address and command to CK | Within ±312.5 ps at TI; AMD Versal asks for ±100 ps on the command bus and ±20 ps on the chip-select and clock-enable lines. | Vendor guide [1] |
| Route delay | Clock, address, strobe and data all stay under 450 ps. AMD Versal gives it as 3600 mil on inner layers only. | Vendor guide [1] |
| Termination | None on the board: everything is point-to-point and terminated on-die. No VTT rail, and no VREF routing either. This is the big difference from DDR4, and it is why LPDDR4 layouts are so much smaller. | Vendor guide [1] |
| Deskew | Per-bit deskew in the PHY loosens the tolerances substantially, which is why LPDDR4 windows are wider than DDR4 ones. | Vendor guide [1] |
| Vias and stubs | Two vias per data trace, three on clock and address, equal counts within a group, via stubs under 20 mil on clock and address and under 40 mil on data. Return vias within 250 mil. Signals with a via near the SoC must not also have a via near the memory. | Vendor guide [1] |
| Spacing | 5W from a clock or strobe to anything else, 3W inside the address group and inside a byte; 2W for up to 500 mil near the ends. | Vendor guide [1] |
| Reference plane | No plane cuts in the routing area, plane directly adjacent to the signal layer, stripline strongly preferred. | Vendor guide [1] |
Check LPDDR4 / LPDDR4X (up to 4266 MT/s) on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
Related guides
- PCB Crosstalk and the 3W Rule: How Much Spacing Is Enough?
- Controlled Impedance Explained: Microstrip, Stripline and Solder Mask
Sources
- TI SPRAD06C — AM62x, AM62Lx DDR Board Design and Layout Guidelines (rev. March 2025). Tables 3-6 and 3-7: 40 Ω / 80 Ω ±10 %, 1.5 ps DQS intra-pair, the −49 to +2 ps data-to-strobe window, 0–150 ps clock-to-strobe ordering, 450 ps route limits, 5W/3W spacing, via and stub limits, and §3.9–3.13 on the absence of VTT and VREF.
- AMD UG863 — Versal Adaptive SoC PCB Design User Guide, LPDDR4/4x rules. 45 Ω single-ended and 82 Ω differential ±10 %, ±100 ps data-to-strobe, 0–2 ps intra-pair, 3600 mil inner-layer routing, and spacing expressed in dielectric heights.
- Efinix UG-PCB-DDR-TI v1.2 — Titanium DDR DRAM PCB Design User Guide. 40 Ω / 80 Ω ±10 % for LPDDR4 and LPDDR4X alike, 75 ps byte skew, 350 ps clock-to-strobe, 250 mil return vias, and 3× width spacing on FR-4 stripline.
Layout guidelines for other interfaces
HDMI · DisplayPort · USB 3.2 · USB 2.0 · DDR4 · RGMII · RMII · SGMII · 1000BASE-T Ethernet · MIPI D-PHY · SATA · PCIe