SATA PCB Layout Guidelines
Route SATA pairs at 100 Ω differential, keep intra-pair skew within 20 ps (vendors route 5 mil), AC-couple with at most 12 nF at 6 Gb/s, and avoid vias and stubs on the pair.
Every rule below names the document it comes from: the SATA specification where it makes the rule mandatory, otherwise a chip vendor’s layout guide. Vendor guides differ, so treat their numbers as good practice and follow your own device’s guide where it is stricter.
Key numbers
| Quantity | SATA 3.0 (6 Gb/s) |
|---|---|
| Line rate | 6 Gb/s |
| Nyquist frequency | 3 GHz |
| Encoding | 8b/10b NRZ, with mandatory down-spread spread-spectrum clocking at 30–33 kHz |
| Impedance | 100 Ω differential (85–115 Ω) |
| Intra-pair skew | 20 ps |
| Longest route | 77.5 mm (3.05 in) |
- The receiver pair must be 85–115 Ω; the cable is held to ±10 % and the mated connector to ±15 %.
Routing rules
One transmit and one receive pair to a drive connector, AC-coupled at both ends.
| Rule | Requirement | Basis |
|---|---|---|
| Impedance | 100 Ω differential. The receiver is specified at 85–115 Ω and at least 40 Ω single-ended. | Specification [1] |
| Intra-pair skew | 20 ps at the transmitter; vendors route the board to 5 mil. | Specification [1] |
| Pair-to-pair skew | None: each direction is a single pair with its own clock recovery, so transmit and receive lengths are independent. | Specification [1] |
| AC coupling | Required at 6 Gb/s: at most 12 nF, and the specification advises against bodies larger than 0603 or values under about 300 pF. It ties the package size directly to a return-loss failure: at 3 GHz the capacitor pad is the discontinuity, not the capacitor. Use 0402 or smaller, void the plane under the pads and keep both capacitors of a pair identical. | Specification [1] |
| Termination | On-die. The transmitter is specified driving into 100 Ω differential, and nothing external belongs on the pair. | Specification [1] |
| Trace length | TI budgets 3050 mil in total on its SoCs, and up to 5500 mil on others. | Vendor guide [2] |
| Vias and stubs | TI budgets no vias and no stubs at all on a SATA pair, and asks for the run on an outer layer next to ground. Any stub over 15 mil must be back-drilled. | Vendor guide [2] |
| Spacing | 30 mil to any other signal, 50 mil to a clock or periodic signal, 90 mil from a plane edge, and package escape completed within 0.25 in. | Vendor guide [2] |
| Cable and connector | The cable must stay inside 100 Ω ±10 % with at most 10 ps of skew and 6 dB of loss to 4.5 GHz; the mated connector is allowed ±15 %. | Specification [1] |
| Connector entry | For a through-hole receptacle, land the pair on the bottom layer so the pin is part of the line rather than a stub. | Vendor guide [2] |
Check SATA 3.0 (6 Gb/s) on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
Related guides
- AC Coupling Capacitors on High-Speed Links: the Value for Every Interface
- Controlled Impedance Explained: Microstrip, Stripline and Solder Mask
Sources
- Serial ATA Revision 3.1, Gold Revision (SATA-IO). Table 35 general specifications (6 Gb/s, unit interval, 100 Ω nominal, AC coupling at most 12 nF, spread spectrum 30–33 kHz down-spread), Table 38 transmitter skew of 20 ps, Table 39 receiver impedance 85–115 Ω and 40 Ω single-ended, Table 20 cable and connector limits, §7.2.2.1.10 on capacitor size and return loss. SATA-IO publishes the Gold revisions free.
- TI SPRAAR7J — High-Speed Interface Layout Guidelines (Feb 2023). Per-interface impedance, intra-pair skew and trace-length limits for TI SoCs (Appendix A), plus the general rules: 5W pair-to-pair spacing, 200 mil ground-via distance, < 15 mil via stubs, ≤ 0603 series parts.
Layout guidelines for other interfaces
HDMI · DisplayPort · USB 3.2 · USB 2.0 · DDR4 · LPDDR4 · RGMII · RMII · SGMII · 1000BASE-T Ethernet · MIPI D-PHY · PCIe