RMII PCB Layout Guidelines
RMII runs every line on one 50 MHz ±50 ppm reference clock, with data valid 4 ns before and 2 ns after its rising edge. Vendors route the lines at 50 Ω single-ended, matched to REF_CLK within 50 mil (TI) and under 6 in.
Every rule below names the document it comes from: the RMII specification where it makes the rule mandatory, otherwise a chip vendor’s layout guide. Vendor guides differ, so treat their numbers as good practice and follow your own device’s guide where it is stricter.
Key numbers
| Quantity | RMII (MAC ↔ PHY) |
|---|---|
| Line rate | 0.05 Gb/s |
| Nyquist frequency | 0.025 GHz |
| Encoding | SDR, 50 MHz REF_CLK, 2 bits per clock per direction |
| Impedance | 50 Ω single-ended (45–55 Ω) |
| Matching to REF_CLK | 1.27 mm (50 mil) |
| Longest route | 152 mm (6 in) |
- Vendor convention: the RMII specification deliberately specifies no impedance.
Routing rules
Reduced MII: two data lines per direction on one shared 50 MHz reference clock.
| Rule | Requirement | Basis |
|---|---|---|
| Reference clock | 50 MHz ±50 ppm, duty cycle 35–65 %, output edges 1–5 ns. | Specification [1] |
| Setup and hold | Data valid at least 4 ns before the rising edge of REF_CLK and held at least 2 ns after it. With a 20 ns period that leaves about 14 ns of slack, which is why RMII matching is loose. | Specification [1] |
| Impedance | None in the specification: it treats the connections as electrically short. Vendors route them as 50 Ω single-ended ±10 %. The specification does ask for the lowest drive strength that works, to keep board noise and EMI down. | Vendor guide [1] |
| Length matching | 50 mil to REF_CLK per TI; Microchip allows 120 mil per port. | Vendor guide [3] |
| Trace length | Under 6 in per vendor guides. The specification only requires drivers to work into 25 pF, which it says covers over 12 in of trace. | Vendor guide [3] |
| Series termination | R = 50 Ω − the driver output impedance, at the driver. | Vendor guide [2] |
| Reference plane | An unbroken plane below (or above) the signals; ground via beside any signal via. | Vendor guide [2] |
| Clock source | REF_CLK comes either from the MAC or from the PHY / an external oscillator. Both ends must agree on which. | Vendor guide [1] |
Check RMII (MAC ↔ PHY) on your own stackup → The interface rules tool designs the trace for this impedance on a layer you choose and turns every limit above into a length on that board.
Related guides
Sources
- RMII Specification Rev 1.2 (RMII Consortium, 20 March 1998). §7.4 AC characteristics (50 MHz ±50 ppm, 35–65 % duty, 4 ns setup, 2 ns hold, 1–5 ns edges, 25 pF load) and §7.2, which states that no characteristic impedance is within the scope of the specification.
- Microchip ENT-AN1231 VSC8541 Design and Layout Guide, VPPD-04420 Rev 1.1. MAC-interface series termination R = 50 Ω − driver output impedance (27–39 Ω on this PHY), 120 mil matching per port, external 1.5–2.0 ns RGMII clock “trombone” delay, Bob Smith on the cable-side centre taps.
- TI SNLA387 — Ethernet PHY PCB Design Layout Checklist (June 2021). MDI and MII trace rules: 100 Ω ±10 % / 50 Ω to ground, 20 mil pair matching at 1 Gb/s, 2 in MDI and 6 in MII length limits, 3W/5W keep-out, 20 mil earth-ground moat, magnetics keep-out, ESD diode placement.
Layout guidelines for other interfaces
HDMI · DisplayPort · USB 3.2 · USB 2.0 · DDR4 · LPDDR4 · RGMII · SGMII · 1000BASE-T Ethernet · MIPI D-PHY · SATA · PCIe