Crystal Load Capacitors & PPM Budget

Method, formulas and references

Load capacitors

In a Pierce oscillator the crystal sees the two load capacitors in series plus the stray capacitance of the pins and traces. The crystal is calibrated by the manufacturer at a stated load capacitance C_L, and the circuit must present that value:

The stray capacitance is usually 2–5 pF; it is not known exactly, so check the frequency on the first boards. E12 and E24 are the IEC 60063 preferred-value series.

Frequency pulling

Using the Butterworth–Van Dyke model (motional capacitance C_m, shunt capacitance C₀), the load-resonant frequency is approximately

so a load capacitance other than the specified one shifts the frequency by C_m/2 · [1/(C₀ + C_L,actual) − 1/(C₀ + C_L,spec)]. A smaller load capacitance raises the frequency.

PPM and drift

For example, a 20 ppm error makes a clock gain or lose 1.728 s per day, about 10.5 min per year.

PPM budget

A crystal datasheet gives its frequency error as separate terms: the tolerance at 25 °C, the stability over temperature and the aging per year. Each is a ± limit. The budget adds them two ways: the worst case adds them linearly, which is what a specification check needs, and the root-sum-square (RSS) assumes they are independent and do not all reach their limits together, which is closer to a typical board.

Aging is counted as the first-year figure plus the per-year figure for every year after it, because crystals age fastest at the start. A life shorter than one year still counts the whole first-year figure.

The fitted capacitors give a load capacitance other than the specified C_L unless the exact value is fitted. Its pulling, from equation (2), is a signed offset that moves the whole error window rather than widening it, so it is added to both totals as it is. The load uncertainty ±ΔC_L (the stray-capacitance estimate and the capacitor tolerance) is a ± term; the larger of the two excursions is used, because the pulling curve is steeper at the smaller load.

A PLL or clock multiplier scales the frequency error with the frequency, so the error in ppm is the same for every clock derived from the crystal. For an oscillator module the datasheet stability usually already combines the initial, temperature, supply and load terms; enter it once.

Two ends of a link

Interface specifications limit each clock against its nominal frequency. Two independent clocks at opposite limits then differ by twice that: two USB high-speed clocks at ±500 ppm may be 1000 ppm apart, and PCI Express allows 600 ppm between the two ends without a common reference clock. The far-end offset shows the worst case for this board against the other end.

UART has no specified tolerance; the limit is derived here for an ideal receiver that finds the start edge within one sample, 1/n of a bit at n× oversampling, and samples the middle of every bit. The middle of the stop bit, 9.5 bits after the start edge for 8N1, must stay inside the stop bit, so the two clocks may differ by at most (½ − 1/n) / 9.5: 4.6 % at 16× oversampling. Receivers that vote over three samples tolerate less, so prefer the figure in the UART datasheet where it gives one.

References

1. E. A. Vittoz, M. G. R. Degrauwe, S. Bitz, "High-performance crystal oscillator circuits: theory and application", IEEE J. Solid-State Circuits, vol. 23, no. 3, 1988.
2. STMicroelectronics AN2867, Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs.
3. IEC 60063, Preferred number series for resistors and capacitors.

Data sources

1. Universal Serial Bus Specification Rev 2.0 (27 April 2000)
   §7.1.11 Data Signaling Rate: 480.00 Mb/s ±500 ppm for high speed, and ±0.05 % (500 ppm) at any speed for hosts, hubs and high-speed-capable functions; 12.000 Mb/s ±0.25 % (2,500 ppm) for full-speed-only functions; 1.50 Mb/s ±1.5 % (15,000 ppm) for low-speed functions. §11.7.1.3: the 500 ppm covers voltage, temperature and aging, so two clocks may differ by 1000 ppm.
2. UNH-IOL Gigabit Ethernet Consortium, Clause 40 PMA Test Suite v2.5 (May 2008)
   Test 40.1.x transmit clock frequency, citing IEEE Std 802.3-2005 clause 40.6.1.2.6: 1000BASE-T symbols are timed from 125.00 MHz ±0.01 % (125 MHz ±12.5 kHz) in both MASTER and SLAVE timing mode.
3. UNH-IOL Fast Ethernet Consortium, Clause 25 PMD Test Suite v3.5 (September 2011)
   Test 25.1.8 Transmit Clock Frequency, citing IEEE Std 802.3-2005 clause 25 and subclause 24.2.3.4: the 100BASE-TX transmit clock is 125 MHz ±6.25 kHz, i.e. ±50 ppm.
4. RMII Specification Rev 1.2 (RMII Consortium, 20 March 1998)
   §7.4 AC characteristics (50 MHz ±50 ppm, 35–65 % duty, 4 ns setup, 2 ns hold, 1–5 ns edges, 25 pF load) and §7.2, which states that no characteristic impedance is within the scope of the specification.
5. PCI Express Base Specification Rev. 2.0 (December 2006)
   §4.3.7.4: Refclk 100 MHz ±300 ppm with spread spectrum off; SSC adds +0 to −5000 ppm at 30–33 kHz. §4.2.7: clocks at the limits give a 600 ppm difference between the two ends of a link, which the SKP ordered sets absorb.
6. PCI Express Card Electromechanical Specification Rev. 3.0 (July 2013)
   §4.7.7 intra-pair skew 5 mil on an add-in card and 10 mil on a system board; §4.7.8 trace impedance 68–105 Ω at 5 GT/s and 70–100 Ω at 8 GT/s, excluding vias, connectors and packages; §4.7.9 750 ps edge-finger delay; Table 4-5 lane-to-lane skew; §4.7.1 AC coupling on the transmit pair; §2.1.1 the 100 MHz ±300 ppm reference clock; §6 removal of the planes under the edge fingers. PCI-SIG membership is needed to download it.
7. Serial ATA Revision 3.1, Gold Revision (SATA-IO)
   Table 35, ftol TX Frequency Long Term Accuracy: −350 to +350 ppm of the nominal rate at 1.5, 3.0 and 6.0 Gb/s; §7.1.1: the receiver accepts ±350 ppm, plus 0 to −5000 ppm of spread-spectrum down-spread.