Phase Noise to RMS Jitter: Why the Integration Band Matters
A phase-noise plot does not have one universal jitter number. RMS jitter depends on the carrier frequency and on the offset-frequency range you integrate. Quote the integration band alongside the result; two numbers calculated over different bands cannot be compared fairly. [1, 3]
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From dBc/Hz to time
Single-sideband phase noise L(f) is a density at an offset f from the clock carrier. Convert each dBc/Hz value to a linear power ratio and integrate it over the chosen offset range. For small phase noise, the RMS phase variation and time jitter are [1]:
The factor of two converts the single-sideband power into total phase variance. The phase-noise level must be converted from dBc/Hz before integrating; adding negative dB numbers is not an integration. [1]
A simple flat-noise example
Suppose a 100 MHz oscillator has a flat −150 dBc/Hz phase-noise density from 1 kHz to 1 MHz. The linear density is 10−15/Hz. Its area is 10−15 × 999,000 Hz = 9.99 × 10−10. The formulas give φrms ≈ 44.7 µrad and σt ≈ 71 fs RMS over that band. This is an illustrative flat spectrum; it says nothing about noise below 1 kHz or above 1 MHz. [1]
Integrate an oscillator phase-noise curve in the jitter tool →
Choosing the band is a design decision
Near-carrier noise can dominate a long integration, while a receiver's clock recovery may track slow fluctuations instead of treating them as eye-closing jitter. An ADC sampling clock has its own input bandwidth and aliasing behaviour. Use the band required by the interface or measurement method; a convenient 12 kHz–20 MHz telecom figure is not automatically the right band for a high-speed ADC or serial link. [1, 2, 3]
Where the jitter number goes next
For a sampled sine at input frequency fin, the jitter-only signal-to-noise limit is SNRj = −20 log₁₀(2πfinσt). Higher input frequencies are more sensitive to the same time jitter. ADC aperture jitter and independent clock jitter add by root-sum-square before this calculation. Serial-link total jitter at a specified bit error ratio uses a different budget and should not be inferred directly from an RMS phase-jitter figure. [1, 2]
Tools used in this guide
- Phase Noise to Jitter & Jitter Budget – RMS phase jitter from an oscillator phase noise curve by exact segment integration, jitter-limited ADC SNR and ENOB, and total jitter at a BER from random and deterministic terms.
- Crystal Load Capacitors & PPM Budget – Crystal load capacitors with the nearest E12/E24 values and the pulling they cause, a ppm frequency budget checked against USB, Ethernet, PCIe and SATA clock tolerances, and ppm ↔ frequency error and drift.
- ADC Input Settling Checker – SAR ADC source and RC filter settling during acquisition, filter-node recovery, and an optional DC accuracy budget for offset, gain, reference, INL and quantisation.
Sources
- Analog Devices MT-008, Converting Oscillator Phase Noise to Time Jitter: integrated single-sideband noise, the factor of two and RMS time jitter.
- Analog Devices, ADC SNR-method FAQ: the jitter-limited SNR formula and why the clock-noise integration bandwidth depends on the sampling system.
- Analog Devices AN-1067, The Power Spectral Density of Phase Noise and Jitter: distinctions between phase-noise spectra and integrated jitter.
Related guides
- Crystal Load Capacitors and PPM Budget: From Picofarads to Clock Error
- RC Filter Design: Choosing R and C for Low-Pass and High-Pass Filters
- PCIe Gen3 Routing on a Hobby Budget: Lessons from an M.2 NVMe Carrier Card
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