Crystal Load Capacitors and PPM Budget: From Picofarads to Clock Error

An 18 pF crystal load specification does not mean fitting two 18 pF capacitors. The crystal sees their series combination plus the effective stray capacitance. Choosing standard parts changes that load and can introduce a frequency offset before temperature and aging enter the budget. ^{[1, 2]}

Calculate the load seen by the crystal

For the model used here, C_S is the effective capacitance in parallel with the crystal after accounting for pins and layout. The external capacitors C1 and C2 connect the crystal terminals to ground:

For equal capacitors C1 = C2 = C, this reduces to C_L = C/2 + C_S, so C = 2(C_L − C_S). If a vendor defines stray capacitance separately at each pin, reduce that network to the same effective parallel definition before inserting its number. Otherwise the stray term can be counted twice. ^{[1, 2]}

Worked example: 18 pF load, 4 pF effective stray

Take an illustrative crystal specified at C_L = 18 pF and assume a 4 pF effective stray load. Each exact capacitor is 2(18 − 4) = 28 pF. These assumptions do not identify a particular crystal or board.

Compare exact and standard load capacitors →

The capacitor value follows from the assumed stray load. A neat arithmetic result cannot establish that the assumption matches the assembled board. Use the oscillator and MCU guidance for placement and pin capacitance, then measure frequency under appropriate loading. Check the measurement probe’s added capacitance too. ^[2]

Estimate frequency pulling when the crystal model is known

Changing load capacitance moves the parallel-resonant frequency. The calculator uses the small-motional-capacitance approximation below, with C_m as motional capacitance and C0 as crystal shunt capacitance. These are different from the external load capacitors. ^[2]

To illustrate the arithmetic, assume C_m = 10 fF = 0.010 pF and C0 = 2 pF. Fitting 27 pF gives an effective 17.5 pF load, so the estimated offset is +6.410 ppm. At 25 MHz, that is +160.26 Hz. Fitting 30 pF instead gives −11.905 ppm, or −297.62 Hz. Replace the model values with the chosen crystal’s data; leave pulling uncalculated when C_m is unavailable.

Keep fixed offsets separate from tolerance limits

One ppm is one part in a million: Δf = f_nom × ppm × 10⁻⁶. A known nominal load-pulling offset is signed; uncertain initial frequency, temperature effects and aging are bounds around it. Adding their absolute maxima gives a conservative worst-case interval.

For an illustrative first-year budget of ±10 ppm initial tolerance, ±20 ppm temperature stability and ±3 ppm aging, the uncertainty sum is ±33 ppm. Add the +6.410 ppm nominal pulling above: the total interval is −26.590 to +39.410 ppm. At 25 MHz it spans approximately −664.74 to +985.26 Hz. This example sets load uncertainty to zero to isolate the terms; a real budget must include the uncertainty of the fitted capacitors and stray load.

Reproduce the signed pulling and first-year ppm budget →

Finish the oscillator check

Load capacitance and ppm do not prove startup. Check crystal ESR, the oscillator’s gain margin, drive level and the device-specific component recommendations. A clock module may already specify a combined stability figure; do not enter that figure and its included terms a second time. ^[2]

For an interface, use the correct clock architecture and specification: absolute clock tolerance and the difference between independent clocks are separate questions. The calculator lists the source behind each supported limit. Frequency tolerance also differs from phase jitter; use the phase-noise tool for the latter.

Check phase noise and jitter separately from the ppm budget →

Tools used in this guide

• Crystal Load Capacitors & PPM Budget – Crystal load capacitors with the nearest E12/E24 values and the pulling they cause, a ppm frequency budget checked against USB, Ethernet, PCIe and SATA clock tolerances, and ppm ↔ frequency error and drift.
• Phase Noise to Jitter & Jitter Budget – RMS phase jitter from an oscillator phase noise curve by exact segment integration, jitter-limited ADC SNR and ENOB, and total jitter at a BER from random and deterministic terms.
• Interface Design Rules – Impedance, skew, loss budget and length limits of PCIe, USB, Ethernet, HDMI, DDR and other interfaces, applied to a layer of your own stackup with the field solver.

Sources

1. NXP, How to calculate the value of crystal load capacitors?: effective load capacitance and the equal-capacitor relation.
2. STMicroelectronics AN2867, Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs: crystal models, load pulling, gain margin, drive level and layout.

Related guides

• Phase Noise to RMS Jitter: Why the Integration Band Matters
• 100 nF or 10 µF? Choosing Decoupling Capacitors for a PCB

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