Through-Hole Padstack Calculator

Plated through-hole sizing after IPC-7251, IPC-2221 and IPC-2222: finished hole, outer and inner pads, antipad, thermal relief and the annular ring achieved, for density levels A, B and C.

Method, formulas and references

A note on names: this calculator labels the density-level values “IPC-7251”, the name land-pattern libraries publish them under. IPC-7251 itself was never released; the committee stopped work on it in October 2014 and moved through-hole land patterns into IPC-7351C (T. Hausherr, PCB Libraries forum, 2014). The through-hole hole and pad size guide traces each value to its source.

Hole

The finished (plated) hole is the maximum lead diameter plus an allowance that depends on the density level. A rectangular lead uses its diagonal √(W² + T²), because the corners must clear the hole.

Feature	Level A	Level B	Level C
Hole over max lead (IPC-2222 / IPC-7251)	0.25	0.20	0.15
Fabrication allowance, IPC-7251 land patterns	0.60	0.50	0.40
Fabrication allowance, IPC-2221 Table 9-1	0.40	0.25	0.20
Thermal ID over hole (IPC-7251 chart)	0.60	0.40	0.30
Thermal OD / antipad over hole (IPC-7251 chart)	1.00	0.70	0.50

All values in mm.

Lands

For a rectangular lead, the preview uses square lands and a square plane antipad around a round hole. Both sides equal the calculated minimum land or antipad size. IPC-2221 permits non-circular land shapes, and IPC-7251 defines the annular ring at its narrowest point. A longer rectangular land is a separate design choice; no lead-aspect extension is calculated. The thermal relief remains round.

IPC-2221 §9.1.1 gives the worst-case land-to-hole relationship:

(1)Land_min = a + 2b + c

Here a is the maximum finished hole (the drilled hole on internal layers), b is the minimum annular ring and c is the fabrication allowance. IPC-2221 Table 9-2 sets the minimum annular ring at 0.05 mm on external layers (supported holes) and 0.03 mm on internal layers. The notes to Table 9-1 add 0.05 mm per oz of copper above 1 oz and 0.05 mm above 8 layers. They are applied when the IPC-2221 basis is selected. IPC-7251 land patterns use larger allowances (0.6/0.5/0.4 mm) and the finished hole for a. The published worked example, a 0.55 mm lead at Level B, gives a 0.75 mm hole and a 1.35 mm pad. The IPC-7251 padstack default repeats the outer land on inner layers. This page reports the larger of that and the IPC-2221 internal minimum.

Planes

IPC-2222 §9.1.2: the total width of the thermal webs should be 60 % of the land diameter, divided among the spokes. The combined web of all planes on one hole should not exceed 4.0 mm for 1 oz copper (2.0 mm for 2 oz). The thermal ID and OD, and the rule that the plane clearance equals the thermal OD, come from the IPC-7251 padstack charts by PCB Matrix (T. Hausherr). They are a library convention, not a requirement of the IPC-2221/2222 text, which leaves thermal geometry to the designer. IPC-2221 §9.1.3 says only that the relationship between hole, land and web is critical.

Unverified defaults (editable)

Drill oversize 0.10 mm. This is a conservative assumption for the plating allowance, not an IPC value. Ask your fabricator; many use 0.05–0.15 mm.
Hole tolerance 0. This matches the IPC-7251 charts, which size the land from the nominal hole. Enter the fabricator’s plus tolerance to apply IPC-2221 strictly.
IPC-7251 fabrication allowances and hole allowances. IPC-7251 itself was not available. These values come from secondary sources that agree with each other: the PCB Matrix chart, EDN and PCB 3D.
Internal annular ring. 0.03 mm is from IPC-2221 (1998) Table 9-2. Secondary sources quote 0.025 mm for IPC-2221B.
Maximum hole-to-lead difference. IPC-2222B Table 9-6 also caps the hole relative to the minimum lead (0.7 mm at Level B, per a secondary source). The page does not check this.

References

IPC-2221, Generic Standard on Printed Board Design, Feb. 1998, §9.1 and Tables 9-1 and 9-2.
IPC-2222, Sectional Design Standard for Rigid Organic Printed Boards, §9.1.2 (thermal relief) and the hole-to-lead tables.
IPC-7251, Generic Requirements for Through-Hole Design and Land Pattern Standard.
T. Hausherr (PCB Matrix), IPC-7251 PTH padstack charts and the IPC-7x51 padstack naming convention.
“Standards for PTH Hole and Pad Diameter sizes”, EDN; “How to calculate PTH hole and pad diameter sizes according to IPC-7251, IPC-2222 and IPC-2221”, PCB 3D.

Related guides

Through-Hole Hole and Pad Size: How Big to Drill for a Component Lead

Related components tools

Home · All tools · Schematic design · Guides · About · Privacy · Terms

All calculators

Signal integrity

Impedance Calculator – Single-ended and differential microstrip, coated and embedded microstrip, stripline, coplanar lines and broadside differential pairs, solved with a 2D field solver.
Propagation Delay, εeff & Timing – Propagation delay, length matching from skew, rise time to bandwidth, critical length and wavelength.
Signal Termination Calculator – Source-series, single-ended load and differential load termination from trace impedance, with E-series values, reflection and resistor stress.
Trace Loss (Insertion Loss) Calculator – Insertion loss in dB/in and over the full length: conductor loss with copper roughness and dielectric loss from the field solver, with laminate Dk/Df across frequency.
Crosstalk Calculator – Near- and far-end crosstalk between parallel traces from the field solver, with a sweep over the spacing (3W rule check).
Differential Via – Via-pair differential impedance through the plane clearance from a 2D field solution, antipad sizing for a target, stub resonance and delay.
Via Stitching & Via Fence Spacing – Stitching and fence via pitch from the wavelength (λ/10, λ/20), via-grid cell resonance, leakage between vias and plane-pair cavity resonances.
Interface Design Rules – Impedance, skew, loss budget and length limits of PCIe, USB, Ethernet, HDMI, DDR and other interfaces, applied to a layer of your own stackup with the field solver.
Phase Noise to Jitter & Jitter Budget – RMS phase jitter from an oscillator phase noise curve by exact segment integration, jitter-limited ADC SNR and ENOB, and total jitter at a BER from random and deterministic terms.
S-Parameter Viewer (.s2p, .s4p) – Open .s1p to .s16p Touchstone files in the browser: insertion and return loss, phase, group delay, mixed-mode SDD21/SCD21 for 4-ports, TDR impedance and interface loss budgets.

Communication interfaces

SPI Timing Calculator – Opposite-edge SPI read timing: clock and MISO path delay, peripheral tCO, setup margin and the timing-limited clock ceiling.
I²C Pull-up Calculator – Pull-up resistor range for Standard, Fast and Fast-mode Plus I²C from bus capacitance, rise time and device sink current.
CAN / CAN FD Bit Timing Calculator – CAN and CAN FD bit timing, sample point, prescaler and segment search with Bosch M_CAN limits, plus standard and split termination.
RS-485 / Modbus RTU Calculator – Two-wire RS-485 end termination, conservative external bias sizing, rise-time-based stub length and Modbus RTU frame and polling timing.

RF

VSWR, Return Loss & Mismatch Loss Calculator – Convert between VSWR, |Γ|, return loss, mismatch loss and reflected power, find Γ of a complex load, and bound the mismatch uncertainty and cascaded VSWR of two ports.
Coaxial Line Impedance Calculator – Characteristic impedance of a coaxial line from D, d and εr, or the diameter for a target Z0, with offset centre conductor, delay, C and L per metre, TE11 cutoff and loss.
L-Network Impedance Matching & Smith Chart – Two-element L-section matching of a complex load: every low-pass and high-pass solution with L and C values, node Q, swept return loss, bandwidth, nearest E-series parts and a Smith chart.
Quarter-Wave Transformer & Stub Calculator – Single and multisection binomial or Chebyshev λ/4 transformers with exact response and bandwidth, open and short stubs, and single-stub matching, with physical lengths and trace widths.

Stackup

Stackup Advisor – Find rigid, flex and rigid-flex region stackups by thickness and layer count, then rank candidates by impedance and solve trace widths.
Layer Stack Manager – 178 rigid fab stackups plus six flex and rigid-flex design starters, with linked regions, editable materials and per-layer impedance.
KiCad Stackup Impedance Calculator – Reads the stackup of a .kicad_pcb file or project folder in the browser, gives 50 Ω and 90/100 Ω differential widths and loss per layer, and checks the impedance, skew and loss of every routed pair.
KiCad Project – The active KiCad project of this browser: stackup, layer roles, net classes, pairs, impedance by layer and routing check, read once and shared with the calculators.
PCB Laminate Materials (Dk / Df) – Datasheet Dk and Df of FR-4, low-loss, RF and flex laminates (Isola, Panasonic, Rogers, Shengyi…) at any frequency, plus solder masks and copper foil roughness.

Thermal

Junction Temperature – Junction temperature from power and the thermal-resistance chain (θJA or θJC + θCS + θSA), and the maximum power for a Tj limit.
Thermal Via Array – Thermal resistance of a via array under a hot pad, with plugged or filled vias, and the temperature drop through the board.
Copper Area for Heat Spreading – How much copper a hot part needs: copper-pour thermal resistance by convection and radiation, junction temperature and the smallest pour for a Tj limit.

Power & conductors

Trace Width, Current & Temperature Rise – IPC-2221: width for a current, current for a width, or temperature rise of a trace, with resistance, voltage drop and loss.
Via Calculator – Via current capacity, resistance, thermal resistance, capacitance, inductance and rise-time impact.
Skin Effect & AC Resistance – Skin depth in copper and the AC resistance of a trace across frequency.
Fusing Current – Current that melts a trace in a given time (Onderdonk), for fault and surge analysis.
Wire Gauge & Voltage Drop – AWG diameter, area and resistance, cable voltage drop and loss, the smallest gauge for a drop limit, and Preece fusing current.
Conductor Spacing (IPC-2221) – Minimum electrical clearance between conductors from IPC-2221 Table 6-1: internal, external, coated, high altitude, assemblies.
Creepage & Clearance (IEC 60664-1) – Minimum clearance and creepage per IEC 60664-1: impulse voltage from mains and overvoltage category, pollution degree, CTI material group, reinforced insulation, altitude.

Power integrity

PDN Impedance Calculator – Target impedance, plane-pair capacitance, decoupling-capacitor resonance and the number of capacitors needed, with a log-log |Z|(f) plot.
EMI Filter Designer – Differential-mode LC, π and ferrite-bead filters: loaded attenuation, parasitics, resonance, RC damping, DC loss and preferred component values.

Power supply

Power Tree Planner – Budget source and regulator currents across cascaded rails and loads, estimate losses, check ratings and record power-up dependencies.
Buck Converter Calculator – Buck power-stage sizing with conduction-mode checks, real inductor and capacitor ratings, IC timing limits and current waveforms across the input range.
Boost Converter Calculator – Boost power-stage sizing with conduction-mode checks, real inductor and capacitor ratings, IC timing limits and current waveforms across the input range.
LDO Regulator Power Dissipation – Linear regulator dissipation, junction temperature, efficiency and dropout headroom, with the maximum load for a Tj limit.
Feedback Resistor Divider – Standard-value R1/R2 for adjustable regulators: the best E12/E24/E96 pairs, output error, FB bias current and worst case with tolerance.

Components

Planar Spiral Inductor – Inductance of square, hexagonal, octagonal and circular PCB spirals (modified Wheeler and current-sheet models), with DC resistance and Q.
Through-Hole Padstack Calculator – Plated through-hole sizing per IPC-7251 / IPC-2221 / IPC-2222: hole, outer and inner pads, antipad, thermal relief and annular ring for levels A/B/C.
Two-Terminal SMD Land Pattern Calculator – Size the two copper pads, pitch, courtyard and solder-mask openings for a chip resistor or MLCC from the exact part dimensions and process tolerances.
BGA Land Pattern – IPC-7351 land diameter for collapsing and non-collapsing BGA balls, with tolerance and courtyard, and escape-routing capacity between lands.
Resistor Color Code Calculator – Value, tolerance and temperature coefficient of 4-, 5- and 6-band resistors from their colours (IEC 60062), and the bands for any value.
SMD Resistor Code Calculator – Decode 3-digit, 4-digit and EIA-96 SMD resistor markings and R/m decimal notation, and find the code for any value.
Capacitor Code Calculator – Decode capacitor markings such as 104K and 2A473J: value, tolerance letter, voltage code, and dielectric codes such as X7R and C0G.

Electronics

Ohm's Law & Power – Enter any two of voltage, current, resistance and power to get the other two.
Reactance & LC Resonance – XL and XC at a frequency, LC resonance, the L or C for a target frequency, and series/parallel LC impedance with Q.
RC Low-Pass & High-Pass Filter Calculator – Passive RC low-pass and high-pass filters with source/load resistance, standard component selection, tolerance bounds and interactive gain and phase plots.
Active Filter Designer – Sallen-Key and MFB low-pass and high-pass filters to 8th order (Butterworth, Bessel, Chebyshev): component values, standard-value response, and op amp GBW and slew-rate requirements.
Op-Amp Gain Calculator – Inverting, non-inverting, difference and summing stages: noise gain, bandwidth, output swing, DC offset, noise and resistor tolerance, with standard-value pairs for a target gain.
Crystal Load Capacitors & PPM Budget – Crystal load capacitors with the nearest E12/E24 values and the pulling they cause, a ppm frequency budget checked against USB, Ethernet, PCIe and SATA clock tolerances, and ppm ↔ frequency error and drift.
555 Timer Calculator – Astable frequency and duty cycle, resistor values for a target frequency, and monostable pulse width, from the TI NE555 equations.
Logic-Level Compatibility Checker – Check worst-case VOH/VOL against VIH/VIL, static noise margins and receiver input-voltage limits.
Comparator Hysteresis Calculator – Inverting and non-inverting switching thresholds: design reference and feedback resistors, choose standard values and check resistor, offset and reference uncertainty.
ADC Input Settling Checker – SAR ADC source and RC filter settling during acquisition, filter-node recovery, and an optional DC accuracy budget for offset, gain, reference, INL and quantisation.
NTC Thermistor Calculator – Beta and Steinhart–Hart models with coefficient fitting, a thermistor divider into an ADC with °C/LSB, series-resistor choice, self-heating, tolerance error and a CSV or C lookup table.
Current-Sense Shunt Selector – Select a shunt from current range and voltage-drop budget, with power, tolerance, TCR and amplifier-offset checks.
Resistor Tools – Voltage divider with best E12/E24/E96 pairs, LED series resistor with power rating, and series/parallel R, C and L.
Attenuator Pads – Matched Pi, T and bridged-T pads with the nearest standard values, their actual loss and return loss, and resistor power.

Utilities

Gerber Viewer & Compare – Inspect one Gerber layout or compare two PCB revisions, choose layers independently and highlight added, removed and common geometry. Files stay on your device.
Unit Converter – Length, copper weight, temperature, power (dBm/W/V) and frequency/wavelength.
Reference Charts – Drill sizes (number, letter, fractional, metric), ISO metric and Unified threads with tap and clearance drills, and the AWG wire table.