KiCad Project

Method, formulas and references

What the project page is

The board you load here becomes the active KiCad project of this browser. The calculators that read it offer a From KiCad Project section in their Properties panel: choose a signal layer, a net class, a net or a differential pair and press Apply, and the tool takes the layer’s cross-section, the class widths or the routed width, gap and length from the project. A tool never changes your inputs until you press Apply. Loading another board replaces the project; when a different board is loaded, you are asked first.

What is stored, and where

Only in this browser. The text of the .kicad_pcb file and, when you loaded one, of the .kicad_pro file are kept in the browser’s IndexedDB storage (database pcbplanner-kicad-project), together with the layer roles you changed. Nothing is uploaded: the files are read on your computer, in a background worker, and no server ever sees them. Other files of a dropped folder (schematics, libraries, backups) are not read and not kept.

The board is not stored in a parsed form. Each time you open the site, the stored text is read again, so the project is there after a reload and on later visits, and a newer version of the reader always reads the file afresh. If the browser blocks storage (some private windows) or refuses a very large file, the project stays loaded only until the tab is closed; the Project panel says which. The project is not synchronised to your board file: after you change the board in KiCad, load it again.

How to remove it

Press Close project on this page: both stored files and the layer roles are deleted at once, in every open tab of the site. Clearing the site data of pcbplanner.com in your browser settings removes it as well. The files on your computer are never changed.

Board view

The Board tab draws the board from the same file: the outline, and on each copper layer the zone fills as KiCad last filled them, the tracks and arcs, the pads of every footprint in their shape and rotation, and the vias with their drill holes. Over the copper it draws the body of each part, its fabrication drawing (F.Fab or B.Fab, else the courtyard), named with its reference once the part is large enough on screen; the Power, Thermal and Clearance tabs draw these too, and always name and brighten the parts they are about (the source and loads of a DC drop, the heat sources, the parts on a high-voltage net). A pad's position is taken from its footprint's position and angle, as KiCad does. The routing check marks where it found something: a gap in a reference plane, a via stub over the guideline, a via without a ground via near it (with a dashed line to the nearest one), and the closest spacing to another signal. Choose a pair or net in the list, a marker on the board, or the board link in the routing check to highlight its copper and zoom to it; a click on a track highlights its net. Problems that belong to the whole route, such as impedance, skew or length, highlight the pair without a marker.

Power view

The Power tab checks one net at a time, power nets first in the list. Track current is the quick, worst-case check: every track and via of the net is taken to carry the whole net current, and its temperature rise is the IPC-2221 curve fit I = k · ΔT^0.44 · A^0.725 (A in square mils, k = 0.048 on the outer layers and 0.024 on the inner ones), the formula of the Trace Width tool, with the copper thickness of each layer from the stackup. A via barrel is treated as the Via tool treats it: a ring of 25 µm plating around the drill, with the outer-layer constant. Tracks within half the allowed rise are green, up to it amber, above it red. The page also gives the IPC-2221 width for the current. The old charts are not exact either way: the IPC-2152 measurements allow about 25 % less current than the IPC-2221 curve on outer layers, while inner traces cool almost as well as outer ones or better, so the inner-layer constant (half the outer one) is conservative. For a track close to its limit, check it in the Trace Width tool with the IPC-2152 fit.

DC drop solves the copper of the net as a resistor network. Choose the source part (the regulator or connector that feeds the net; the part with the most pad area on the net is offered first) and the parts that draw current, with their currents. On every layer with a zone of the net, the zone fills and pads are cut into square cells; neighbouring cells are joined by the sheet conductance t/ρ times the part of the cells that is copper, so a neck or a thermal spoke narrower than a cell keeps its own resistance. Within 0.8 mm of every pad of the source and the loads the cells are split to about 0.03 mm, so the thermal spokes and gaps the whole current goes through are resolved. Every track is a resistor ρ·L/(W·t) between its ends (a track that ends inside a via's ring, overlaps another track's end, or ends on the middle of another track is joined there, as KiCad joins copper by overlap); a via or a plated hole is a barrel resistor between neighbouring copper layers, over the height between the layers from the stackup. A pad is one node on each of its layers, and a track or via joins a zone over its own width, not at one point. The source pads are held at the reference, each load draws its current spread over its pads, and the network is solved by conjugate gradients with an aggregation multigrid preconditioner. ρ is annealed copper's 1/58 Ω·mm²/m at 20 °C with a temperature coefficient of 0.393 %/°C, taken at the ambient plus the allowed rise, the hottest the copper may get.

The result is the drop at every load (the mean over its pads), the copper loss, the real current and IPC-2221 rise of every track and via, and a heat map on a chosen layer of the drop or of the sheet current density in amperes per millimetre of width (its colours span 99 % of the copper; the few hottest cells by the vias and pads are shown at the top colour). A load the copper does not connect to the source is named and draws no current. The drop between two places changes by a few per cent with the grid, mostly through how a via meets a plane, so read the result to that accuracy. What is not modelled: the resistance inside the parts and their pins, solder, plating on the outer layers, temperature that varies over the board, and AC effects (decoupling, inductance).

The current comes back through the return net. By default it is the ground net that reaches the source and the most loads (choose another, or none, under Return net). The return is solved the same way, with each load's current flowing from its pads on the return net back to the source's: the load sees the supply drop and the return drop added, and the table gives both and their total. A load with no pad on the return net returns its current some other way (through another part), so its total is left out; a source with no pad on the return net cannot be solved for the return. The map shows either net's copper.

Thermal view

The Thermal tab solves the steady temperature of the whole board from the power of the parts you enter. The board inside its outline is cut into square cells, the same on every copper layer; a cell of a layer stands for its copper and half the laminate on each side of it. Neighbouring cells of a layer are joined by k_Cu·t·c + k_xy·d, where c is the part of the cells that is copper (the zones, tracks, pads and via pads of every net), t the copper thickness and d the laminate the cell stands for; a cell is joined to the same cell of the next layer through the laminate, k_z·A/h, and through every via and plated hole there, k_Cu·a/h for its 25 µm copper ring. The copper of a board conducts 385 W/m·K (Graebner measured 385 ± 15 in boards; pure annealed copper is about 400); the laminate defaults to 0.8 W/m·K along the board and 0.35 through it, and both can be changed. A part's power enters the board through its pads on its own side. With Add the copper loss ticked, the DC drop set up on the Power tab is solved as well and its I²R (the tracks, planes and vias of the supply and of the return net) heats each layer where it is lost; the result names the watts added per net.

The two faces give the heat to the air by convection and radiation. In still air the convection comes from the natural-convection correlations of the heat-spreading tool (hot upper face 0.54·Ra^1/4, lower face 0.52·Ra^1/5 with L = area/perimeter; Churchill–Chu for an upright board). The free textbook of Lienhard gives other correlations of the same kind: Raithby and Hollands for the upper face (with its correction for thick boundary layers, 7 % below the value here for a 31 cm² board) and Fujii and Imura for the lower face, stated for larger plates (Ra ≥ 10⁶) than most boards. With them that board's faces would lose about 10 % less heat, and its rise would be about 10 % higher: a measure of how well the convection of a small board is known. For moving air you enter the convection coefficient. Radiation is εσ(T_s² + T_a²)(T_s + T_a), about 6 W/m²K near room temperature, as much as still-air convection. Both depend on the temperature; since all the heat leaves through the faces, their mean rise is P / ((h_top + h_bottom + 2h_r)·A), and the coefficients are iterated on it before the board is solved once. For a 31 cm² board 34 °C above ambient this gives about 14 W/m²K a face with radiation, against the empirical 15 W/m²K for still air in onsemi's AND9596.

The result is the temperature on every layer (the map's colours span the coolest to the hottest point of the board), the hottest point, and the board temperature under each part (the highest of its pad cells). With the part's ψJB from its datasheet, the junction is T_J = T_PCB + ψ_JB·P, as TI's SPRA953 defines it; θJB is a different, cold-plate measurement and does not belong in that formula. The tests check a well-spreading plate against P / (2hA), a heated copper strip against the exact fin solution, and a hot pad in a copper pour against the heat-spreading tool (within 7 %). Not modelled: heat leaving the top of a package straight to the air (so the parts come out a little hot), enclosures, heatsinks and neighbouring boards, air that warms as it passes, and time (the result is the steady state). Read the temperatures to about ±20–30 %; the differences between two layouts of the same board are more reliable.

Clearance view

The Clearance tab checks the nets you give a voltage (the peak voltage to the circuit's 0 V; nets you leave out are taken as 0 V) against the copper of every other net on the same layer. Each piece of copper is measured exactly: a track as its centre line and half its width (an arc as chords that stay within 1 µm of it), a via or a round pad as its centre and radius, any other pad and every zone fill by the edges of its outline. The closest gap between two nets is set against the spacing IPC-2221 Table 6-1 gives for the peak voltage between them: column B1 on inner layers, and on the outer layers B2 for a bare board or B4 with a permanent polymer coating, as you choose. Between 15 V and 500 V the table steps in bands; above 500 V it adds a fixed amount per volt (B1 0.0025 mm, B2 0.005 mm, B4 0.00305 mm). Each place that is too close is listed and marked on the board with a line across the gap. The zones are measured as KiCad last filled them, so fill the zones before you load the board.

Not checked: spacing between layers through the laminate, creepage along the surface around slots and parts, the coated-assembly columns A5 to A7 and boards used above 3050 m (the Conductor Spacing and Creepage tools cover those), and safety standards that ask for more than IPC-2221, such as IEC 62368-1 for mains equipment. The Table 6-1 values are those of the Conductor Spacing tool, checked for B1, B2 and B4 against two free reproductions of the table.

Net classes and pairs

The net class table lists the classes of the project file with their track width and differential-pair width and gap, and the number of routed nets (nets with tracks) and pairs for which each class decides. Without a project file every net is in Default.

What is read from the file

A .kicad_pcb file is a text file of nested lists (s-expressions). The page reads it in your browser, in a background worker, and looks only at the top-level items it needs: the file version, (general (thickness …)), the (layers …) list, the (stackup …) section inside (setup …), the Edge.Cuts outline graphics, the header, outline and fill polygons of every (zone …), every track segment and arc (start, mid and end point, width, layer, net) and every via (position, layers, net). Footprints and everything else are skipped, so a board of tens of megabytes is read in about a second. Nets are named by their (net N "name") declarations in KiCad 6 to 9 and by (net "name") on each item from KiCad 10. From a .kicad_pro file, dropped with the board or found in the project folder, only the net classes are read; everything else in the folder is ignored.

Each stackup item is (layer "name" (type "…") …) with (thickness mm [locked]), (material "…"), (epsilon_r …) and (loss_tangent …); a dielectric made of several plies lists them as sublayers separated by the bare token addsublayer. Every sublayer becomes its own ply here, so stacked prepregs with different Dk are modelled as they are. Where a value is missing, KiCad's own default is used and listed under the table: Dk 4.5 and loss tangent 0.02 for a dielectric, Dk 3.3 for solder mask, 0.035 mm copper. A mask without a loss tangent uses 0.027, a typical LPI mask. A dielectric with exactly Dk 4.5 and loss tangent 0.02 is flagged, because those are the values KiCad gives every new dielectric.

Plane layers

KiCad does not mark which copper layers are planes, so they are inferred. For each copper layer and net, the area of the net's zones is measured: each zone is its outline less its cut-outs (KiCad saves the cut-outs as further polygons after the outline), zones of the same net that overlap count once, and only the part inside the board outline counts (its bounding box when Edge.Cuts has no closed shape). The board area is the largest closed Edge.Cuts outline (or its bounding box). A layer is taken as a plane when

• it is declared a power layer in Board Setup → Board Editor Layers, or
• zones of at most 3 nets cover at least 50 % of the board, and the layer carries less than 20 % of the track length of the most-routed layer, or
• on a two-layer board, zones cover at least 50 % of one side and less than that of the other.

A ground pour on a busy signal layer therefore stays a signal layer. Each layer's detected role and the reason are shown under Layer roles in the Properties panel, where you can change it. Zone outlines are used, not the filled copper, so antipads and clearances do not reduce the coverage; the fills are used for the reference-plane check below.

Impedance and loss

The stackup is converted to the site's stackup model and every signal layer is handed to the same code as the Layer Stack Manager: the cross-section runs from the trace to the nearest plane above and below; a signal layer passed on the way counts as dielectric (dual stripline). Widths are solved with the site's 2D field solver at normal accuracy with a 0.5 mil trapezoidal etch, so the numbers equal the Layer Stack Manager's impedance view for the same stackup and pair gap. The solves run in parallel on the solver worker pool and are cached for the visit.

Loss per inch is the conductor loss (skin effect with Hammerstad roughness for the chosen foil) plus the dielectric loss from the field solution, as on the Trace Loss and Interface Rules pages. Each ply keeps its own Dk and loss tangent from the file; Dk is moved to the loss frequency with the Djordjevic–Sarkar wideband model, taking the file's values as given at 1 GHz (KiCad's default specification frequency) unless the file states another frequency. For a differential pair the loss is that of the odd mode, which is the differential insertion loss per inch.

Routing check

Net classes. They are read from net_settings in the .kicad_pro file and resolved as the KiCad version that wrote the file does (the schema version is in net_settings.meta.version). KiCad 6 lists the member nets of each class by name. KiCad 7 and 8 use an explicit netclass_assignments entry, else the first matching netclass_patterns entry, else Default. KiCad 9 and 10 apply every assigned and every matching class; the one with the lowest priority number decides and missing values come from the next. A pattern matches when it matches the whole net name either as a regular expression or as a wildcard (* any run, ? one character), case-sensitive, as KiCad's net-class matcher does; vector buses such as D[0..7] are expanded. Without a project file every net is in Default.

Differential pairs. KiCad's own rule: reading the net name backwards, digits and underscores are skipped and the next character must be + or P (positive) or - or N (negative); the partner has that character swapped. So USB_D+/USB_D-, PCIE_TX0_P/PCIE_TX0_N and LVDS_P1/LVDS_N1 are pairs; lower-case p/n are not.

Width and gap. On each layer the width is the length-weighted most common track width of each net, with the range when it varies. Arcs count with their true length. For the gap, every piece of one trace is compared with the pieces of the other trace on the same layer that run within 10° of parallel; a uniform grid of the pieces keeps this fast on large boards. Where the two overlap when projected onto each other (as in KiCad's diff-pair DRC), the centre distance is taken at the middle of the overlap and the gap is that distance less half of each width; where several pieces overlap, the nearest counts. Arcs are cut into chords of at most 2°. The gap reported is the length-weighted most common gap (in 1 µm steps). A section whose gap is more than 3 × that gap (and more than 25 µm above it), or that has no parallel partner at all, such as the breakout to pads and vias, is uncoupled: it is left out of the gap and shown as the difference between coupled and total length. The coupled length is the mean of what is measured along each of the two traces.

Impedance. The measured width and gap of each layer are analysed with the same 2D field solver, cross-section, 0.5 mil etch and accuracy as the width table above, so a width designed for a target and then analysed gives the target back. A pair whose two traces differ in width is solved with their mean. A layer is checked when it has at least 3 mm of coupled length; shorter sections are breakout near pads and vias (and electrically short) and are listed, not checked. A layer with less than 1 mm coupled over more than 5 mm of routing is a warning: the two traces run apart there. The solves run on the solver worker pool and are cached by layer, width and gap.

Length, skew and loss. The length of a net is the sum of its segments and arcs on all layers; the via count is the number of vias on the net. Intra-pair skew is the difference of the two routed lengths; via barrels, pad-to-die (package) lengths and any length-tuning settings in KiCad are not included. It is turned into picoseconds with the delay of the layer that carries the pair (from the solver's effective permittivity of the odd mode). Loss is each layer's routed length times its loss per inch at the interface's Nyquist frequency (the page's loss frequency for a plain impedance target), from the same loss model as the width table and the Interface Rules page.

Gaps in the reference plane. KiCad saves the copper of every filled zone in the board file: the zone less its cut-outs, the clearances to other nets, the antipads and the removed islands. Those fills are rasterised on a 50 µm grid (coarser on a very large board) and every track is sampled along its length against the fills of the other copper layers. A stretch of a trace with no copper under it on one of its reference planes is a gap; stretches are joined across the corners of the trace. A stretch that reaches a pad or a via (a free end of the net's routing on that layer) is left out, because the antipad of the via and any voiding under a connector pad are there by design. What remains is a trace crossing a split, a slot cut by a track routed on the plane layer, a row of merged antipads or a keepout. A gap of 1 mm or more makes the layer a warning, with the total length, the longest gap and where it is in the board's coordinates. The fills are read as they were saved, so refill the zones (B in the PCB editor) before saving the board; layers without fills are not checked.

Layout guidelines. Where the interface's sources give a number, a pair is also checked for via stubs, return vias, via count, lane-to-lane matching and spacing. Each number was read in a free vendor document, which the reason names (TI SLLA414 for USB 3.x, HDMI, DisplayPort, PCIe Gen 3/4 and SATA; TI SLAAE45 and SNLA426 for PCIe; TI SPRAAR7J for USB 2.0 and SATA; TI SPRACP4A and DS90UB936-Q1 for MIPI D-PHY; TI SNLA387 for 1000BASE-T; the TI TMDS1204 and TDP0604 data sheets and the TI HDMI Design Guide for HDMI), and the Interface Rules page lists them per interface. They are recommendations, not limits of the specifications, so a pair outside one is a warning, never a fail; the one exception is lane-to-lane skew beyond what the HDMI specification allows.

• Via stubs. At each via the layers the signal uses are the ones where one of its tracks ends on the via. The stub is the rest of the barrel: from the far face of the outermost used copper to the outer face of the via's last copper layer, summed from the stackup's thicknesses. Removing unused pads does not shorten it. Back-drilled vias, blind and micro vias (by their own layers) and vias the net reaches from one layer only (through a pad or a zone) are not given a stub that is not there.
• Return vias. Where a pair moves to a layer that shares no reference plane with the one it leaves, the nearest via of a ground or plane net must be within the interface's distance of each signal via (centre to centre). A change between two layers that share a plane, such as a microstrip and the stripline below it, needs none.
• Via count. The vias on each trace against the interface's most vias per trace, and whether both traces have the same number.
• Lane-to-lane. Pairs of one link are found by name: the pair name without the lane at its end (D0, D1, CLK, CK, C, TX0, TXC, LANE2), so HDMI_D0, HDMI_D1, HDMI_D2 and HDMI_CLK are one link. Each lane is compared with the shortest lane of its link, in length and through the layer delay in ps. HDMI is checked against 1 in on a source board and fails beyond 0.2 of a character time; MIPI D-PHY against 40 ps. PCIe lane skew comes from a specification that is not freely available and is not checked.
• Spacing. Both traces are sampled every 100 µm and the nearest track of another net on the same layer is found, edge to edge. The pair's own partner and ground and plane nets (guard traces and pours) do not count, and samples within 2.5 mm of a pad or via are breakout and are left out. Another pair is held to the pair spacing (5W, or 30 mil for 1000BASE-T), any other signal to the signal spacing (30 mil). A trace closer than that over 2 mm or more is a warning, with the nearest neighbour and where it is.

Targets and results. Each net class, split by the interface its names suggest, is matched to a target: an interface from the Interface Rules data, or a plain impedance. The suggestion comes from the class and net names (USB, HDMI, PCIe, SATA, MDI/ETH, MIPI/CSI/DSI, …); an impedance written in the class name, such as 85Ohm_PCIE, is the designer's target: the interface is suggested when that impedance lies inside its range and within 10 % of its nominal impedance, otherwise the class's impedance is suggested as a plain target. Change any of them under Routing targets; the choice is kept in the page address. An interface target uses its impedance range from the specification or vendor guide; a plain or custom target allows ±10 %. Skew is checked against the interface's intra-pair limit (a time limit through the layer delay), length against its maximum length and loss against its loss budget (over 80 % of the budget is a warning), where the data has them. Length limits and loss budgets are vendor or informative figures, so a pair over one warns and does not fail. Where the skew limit is a vendor's layout guideline rather than the specification's (HDMI, USB, 1000BASE-T, SGMII), a pair over it is a warning, and a fail only beyond the skew the specification itself allows. ✓ passes, ⚠ needs a look (no reference plane, a gap in it, long uncoupled sections, a tight loss budget, skew or a via, lane or spacing figure outside a guideline), ✗ fails. When the impedance of one net differs by more than 10 % between layers, or one layer passes and another fails, the layer change is flagged: a width that is right on an outer layer is often wrong on an inner one.

Limits

• One project at a time. Loading a board replaces the one that was loaded.
• The inputs of this page (targets, pair gap, loss frequency, routing targets) are kept in its address, like any calculator; the layer roles are kept with the project.
• The routing check measures tracks, not pads: the length inside pads, via barrels and package lengths are not counted, and a track ending on a pad is not joined to the next one. Coplanar ground beside a pair and the copper of other nets near it do not enter the impedance.
• Custom DRC rules (the .kicad_dru file) are not read. Bus groups such as {A B} in net-class patterns are not expanded.
• KiCad 5 and older files have no stackup section (only a board thickness), so no impedance can be given. Open them in KiCad 6 or later, check the physical stackup and save, or enter the layers in the Layer Stack Manager.
• Solder mask is taken as a uniform coating over the outer layers with the thickness in the file over the laminate and half of it over the trace. Switch it off for mask-free areas.
• Coplanar ground beside the trace and the copper roughness of each layer are not read from the file. A gap in a reference plane is reported, but the impedance is solved over a solid plane.
• KiCad's default stackup values are a placeholder; get the pressed thicknesses and laminate Dk/Df from your fabricator.

Sources

1. KiCad source, board_stackup.cpp: BOARD_STACKUP::FormatBoardStackup (how the stackup is written) and the defaults of a new stackup item.
2. KiCad source, pcb_io_kicad_sexpr_parser.cpp: PCB_IO_KICAD_SEXPR_PARSER::parseBoardStackup (how KiCad reads it back).
3. KiCad source, pcb_io_kicad_sexpr.h: the board file format versions.
4. KiCad developer documentation, board file format.
5. KiCad source, net_settings.cpp: NET_SETTINGS, the net classes in the project file, their schema migrations (version 2 in KiCad 6, 3 in KiCad 7 and 8, 4 in KiCad 9, 5 in KiCad 10) and GetEffectiveNetClass.
6. KiCad source, eda_pattern_match.cpp: EDA_COMBINED_MATCHER for net-class patterns (anchored regular expression or anchored wildcard).
7. KiCad source, board.cpp: BOARD::MatchDpSuffix, the differential-pair naming rule.
8. KiCad source, drc_test_provider_diff_pair_coupling.cpp: how KiCad's DRC finds the coupled sections of a pair (parallel projection of segment pairs).

Data sources

1. CircuitCalculator.com, PCB Trace Width Calculator
   The IPC-2221 curve fit of the Power tab: I = k·ΔT^0.44·A^0.725 with k = 0.048 (external) and 0.024 (internal), A in square mils, fitted to the IPC-2221 (IPC-D-275) charts.
2. D. G. Brooks with J. Adam, "Trace Currents and Temperatures Revisited", UltraCAD Design, April 2015
   IPC-2152 against the IPC-2221 charts: about 25 % lower currents for external traces, and internal traces that cool almost as well as external ones or better (introduction).
3. onsemi AND9596/D, "A Quick PCB Thermal Calculation for Power Electronic Devices with Exposed Pad Packages", Rev. 1, 2017
   Pp. 1–2: an empirical heat transfer coefficient, convection and radiation together, of 15, 30 and 45 W/m²K for air at 0, 1.0 and 2.5 m/s; Table 1: FR-4 0.35 W/m·K. The still-air check of the Thermal tab and the default through-plane conductivity.
4. J. E. Graebner, "Thermal Conductivity of Printed Wiring Boards", Electronics Cooling, October 1995
   Copper in boards 385 ± 15 W/m·K; a bare FR-4 board 0.81 W/m·K in-plane (sample PC5). The copper and in-plane laminate values of the Thermal tab.
5. Isola 370HR laminate and prepreg data sheet
   P. 2: thermal conductivity 0.4 W/m·K (ASTM E1952), an example of a laminate datasheet value for the through-plane field.
6. J. H. Lienhard IV, J. H. Lienhard V, A Heat Transfer Textbook, 6th ed., Phlogiston Press (free edition)
   Eqs. 2.29–2.31: linearised radiation, about 6 W/m²K near room temperature; §8.3–8.4: Churchill–Chu for vertical plates, eqs. 8.37a–b (Raithby–Hollands) and 8.38 (Fujii–Imura) for horizontal plates, the comparison in the Thermal view; Table 10.1: emissivities.
7. A. Gorev et al., "Emissivity of printed circuit boards", IOP Conf. Ser.: Mater. Sci. Eng. 734 (2020) 012027 (open access)
   Table 1: measured emissivity of solder-masked boards 0.88 (red) to 0.97 (black), polished copper 0.08; the default ε = 0.9.
8. Texas Instruments SPRA953D, "Semiconductor and IC Package Thermal Metrics", 2024
   §5: ψJB, and eq. 9, T_J = T_PCB + ψJB × Power, the junction estimate of the Thermal tab.
9. smpspowersupply.com: IPC-2221B PCB trace spacing / clearance by voltage (L. Rozenblat)
   Columns B1, B2 and B4 of IPC-2221B Table 6-1, the spacings of the Clearance tab, with the per-volt formula above 500 V and worked rows to 5000 V (the standard itself is sold by IPC).
10. PCBSync: IPC-2221 explained (Table 6-1, IPC-2221B)
    A second reproduction of columns B1, B2 and B4; all nine bands agree with the first.
11. NBS Handbook 100, Copper Wire Tables (1966)
    International Annealed Copper Standard: 1/58 Ω·mm²/m at 20 °C and a temperature coefficient of 0.00393 per °C, the resistivity of the DC drop.