Guides›100 nF or 10 µF? Choosing Decoupling Capacitors for a PCB

100 nF or 10 µF? Choosing Decoupling Capacitors for a PCB

23 September 2026 · 8 min read · pcbplanner

There is no universal choice between 100 nF and 10 µF. Start with the IC's supply requirements, then check the effective capacitance and mounted impedance. The smaller value has a higher self-resonant frequency if the inductance is the same; the larger value stores more charge. Neither fact by itself tells you which arrangement gives the lower supply impedance across the frequencies that matter.

A useful design question is: how much may the rail move, how quickly does its current change, and what impedance does the complete path present? This guide compares two explicit capacitor models so those trade-offs can be reproduced.

What a real decoupling capacitor looks like electrically

A first-order model is a capacitance C in series with resistance ESR and inductance L. Here L is the mounted inductance, including the capacitor and its connection path. Its impedance magnitude and series-resonant frequency are:

|Z(f)| = √[ESR² + (2πfL − 1/(2πfC))²]; fSRF = 1 / (2π√(LC)).

Below resonance the capacitive term dominates. At resonance the reactances cancel and the impedance reaches ESR. Above resonance the inductive term grows. This is why a capacitance value alone cannot describe high-frequency decoupling. TI presents this series-RLC model in its decoupling training. ^[1]

100 nF versus 10 µF: a numerical comparison

Assume both capacitors have 20 mΩ ESR and 1 nH of mounted inductance. Use their effective capacitances as 100 nF and 10 µF. These are illustrative lumped models, not measurements or specifications for a particular package. Holding ESR and L equal isolates the effect of capacitance.

Quantity	100 nF	10 µF
Series resonance	15.92 MHz	1.592 MHz
\|Z\| at 1 MHz	1.585 Ω	0.0222 Ω
\|Z\| at 10 MHz	0.0984 Ω	0.0644 Ω
\|Z\| at 100 MHz	0.613 Ω	0.628 Ω

At 10 MHz the 10 µF capacitor is already inductive but still has the lower impedance. Near 15.92 MHz the 100 nF capacitor reaches its 20 mΩ minimum and wins instead. By 100 MHz both are dominated by roughly the same inductance. A higher self-resonant frequency does not mean lower impedance at every frequency.

Load the 100 nF model at 10 MHz →

Compare the 10 µF model at 10 MHz →

Read the calculator's single-capacitor impedance for the table values. Its total PDN result also includes the plane capacitance, so that is a different quantity.

Why adding both values can produce antiresonance

Between the two series-resonant frequencies, one branch can be inductive while the other remains capacitive. Their susceptances can cancel, producing an impedance peak in the parallel combination. Adding capacitance can therefore raise the impedance over part of the band. TI demonstrates this effect, and Murata shows how connection inductance influences it. ^{[1, 2]}

For the two equal-inductance models above, the susceptances cancel at approximately 11.31 MHz. At that frequency each capacitor alone has about 0.0725 Ω impedance, but the two in parallel give about 0.131 Ω. These numbers come from adding the complex branch admittances, not the impedance magnitudes.

This example excludes planes, regulator, package and shared connection inductance. It demonstrates one possible resonance, not a prediction for every 100 nF plus 10 µF combination. Real ESR and other losses change the peak. Identical parts on equivalent connections avoid this particular separation of resonant frequencies, but different mounting paths and the rest of the PDN can still introduce resonances. ^[2]

A mixed capacitor bank can be appropriate when it is designed for the device and checked across frequency. The useful rule is to verify the combined impedance, rather than assume that each added value fills a harmless gap.

Set a target from the rail's noise budget

A first estimate is Ztarget = ΔV / ΔI. For a 3.3 V rail with 3 % allocated to the transient excursion, ΔV = 99 mV. A 1 A load step gives a target of 0.099 Ω. This allocation needs to fit inside the device's supply limits after allowing for regulator accuracy, DC drop and other noise.^[4]

At 10 MHz, either single-capacitor model in the table is just below that illustrative target, although the 100 nF model has almost no margin. At 100 MHz both are above it. Passing at one chosen frequency therefore does not establish that the rail meets its transient requirement.

The PDN Calculator places identical capacitors in parallel with an ideal plane capacitance. It is useful for exploring count, mounted inductance and the frequency response, but it does not model the mixed bank calculated above. Its count estimate at one frequency is a starting point; its plot also needs checking. Regulator response, package and on-die capacitance, shared inductance and capacitor positions need a fuller model where they affect the result.

Use the capacitance available at the working voltage

High-permittivity ceramic capacitors such as X5R and X7R can lose capacitance under DC bias. The amount depends on the specific part and voltage; the dielectric label and voltage rating alone do not give the remaining capacitance. Consult the manufacturer's bias curve, including temperature and tolerance where relevant. ^[3]

For example, if a nominal 10 µF part has 4 µF effective capacitance in your application, enter 4000 nF in the calculator. With the same assumed 1 nH, its series resonance becomes approximately 2.52 MHz. That 4 µF is an example input, not a generic derating factor for all 10 µF capacitors.

Placement and bulk capacitance

Short, wide connections and a compact supply-to-ground loop reduce the inductance added by the layout. A capacitor placed close to a pin can still have a long electrical path if its ground connection takes a detour. Murata's examples explicitly include the installation pattern when comparing impedance. ^[2]

The charge requirement is a separate check: C ≥ ΔI × Δt / ΔV for a capacitor supplying a constant extra current over Δt. Supplying 0.1 A for 10 µs while allowing 0.1 V of droop requires 10 µF of effective capacitance in that ideal calculation. Real behaviour also includes the regulator's response, the immediate ESR voltage step and inductive effects. Local bypassing and bulk energy storage both need consideration, even when the final selection happens to use the same capacitor value.

A practical selection sequence

Follow the IC and regulator requirements for capacitance, ESR, pin placement and supply stability.
Allocate the allowed voltage excursion and estimate the load-current change and relevant time scales.
Choose actual capacitor parts using effective capacitance and frequency-dependent manufacturer data.
Include the mounting path and inspect the combined impedance across the required band, especially any peaks.
Check transient behaviour at the load pins on the assembled board before relying on a small calculated margin.

Explore four identical capacitors and the plane in the PDN tool →

Tools used in this guide

PDN Impedance Calculator – Target impedance, plane-pair capacitance, decoupling-capacitor resonance and the number of capacitors needed, with a log-log |Z|(f) plot.