Buck Converter Calculator
Size a buck power stage and check real inductors, capacitor banks and IC limits across the input-voltage range, with conduction-mode checks and current waveforms.
Method, formulas and references
Model and operating limits
This is a preliminary continuous-conduction buck design based on TI SLVA477B. Efficiency is a user estimate: D = Vout/(ηVin), so the converter also covers its own losses. This efficiency-adjusted duty is a sizing approximation, not a device-specific switching simulation. In a buck the inductor's average current equals the load current at every input voltage.
The initial inductance follows TI: ΔIestimate = ripple ratio × Iout; L = Vout(Vin,nom − Vout)/(ΔIestimate fs,min Vin,nom). Enter the actual part value before finalising a design. Current screening uses Lmin = L(1 − tolerance) and fs,min. Inductance reduction under DC current, temperature and saturation must be included in the effective minimum value you choose.
ΔIL grows with input voltage, so ripple, peak current and the CCM boundary are worst at Vin,max. CCM requires Ivalley > 0, i.e. a load above ΔIL/2. Boundary/DCM operation and forced-PWM reverse current are not solved. If any point in the checked range leaves CCM, range-wide current and capacitor results are withheld.
Capacitors and ripple
Ceff = Cnom × (1 − tolerance) × retained fraction. Retention is taken from the selected capacitor's voltage and temperature data; it is not inferred from an X5R/X7R label. Enter complete-bank capacitance, ESR and RMS ratings. A value of zero for the bank means sizing only.
The output capacitor sees only the triangular inductor ripple: Cout,min = ΔIL/(8 fs ΔVout), Icout,rms = ΔIL/√12, and ESR ripple = ESR × ΔIL. The sum of capacitive and ESR ripple is a conservative upper bound, since their extrema need not coincide; ESL spikes are excluded.
The input capacitor carries the pulsed switch current minus its average, which makes it the harder-working capacitor in a buck:
The RMS current peaks at D = 0.5, so that input voltage (Vin = 2Vout/η) is always evaluated when it lies inside the range. Input ESR ripple is bounded by ESR × Ipeak, the current step at turn-on. The displayed minimum is the larger of the charge-balance estimate and the IC datasheet minimum. Source impedance, cable inductance, start-up and load transients can demand substantially more capacitance. Output capacitance must also stay within the IC's compensation/stability recommendations.
Rating checks and range screening
The input range is sampled at 201 evenly spaced voltages plus the nominal input and the 50 % duty point. Checks apply at the entered load and constant efficiency, not a full load/temperature sweep.
Current-limit ceiling = Ilim,min − ΔIL/2 at the worst-case ripple, for peak-current-limited ICs and only where the limit exceeds ΔIL. This excludes thermal limits, start-up and protection behaviour. A saturation-current check at operating peak does not certify survival at the maximum IC current limit.
Shortest on-time = Dmin/fs,max at Vin,max; shortest off-time = (1 − Dmax)/fs,max at Vin,min. The minimum on-time is the usual limit for high step-down ratios at high frequency. The switch is screened against Vin,max + Vf (the switch node swings from Vin to −Vf) and the diode against Vin,max. Voltage-rating passes cover steady state only; additional transient and ringing headroom is required. Unspecified ratings remain unchecked.
Total estimated loss = Pout(1/η − 1). Winding I²R, capacitor ESR and diode losses (Vf × Iout(1 − D), largest at Vin,max) are a partial breakdown of that budget, never added to it. MOSFET conduction/switching loss, inductor core loss and thermal behaviour are not separately modelled.
References
- TI SLVA477B — Basic Calculation of a Buck Converter's Power Stage, 2015. Equation 1 of the main text is used; the appendix prints η in the numerator.
- R. W. Erickson, D. Maksimović, Fundamentals of Power Electronics, Springer — input-capacitor RMS current including the inductor ripple.