Boost Converter Calculator
Size a boost power stage and check real inductors, capacitor banks and IC limits across the input-voltage range, with conduction-mode checks and current waveforms.
Method, formulas and references
Model and operating limits
This is a preliminary continuous-conduction boost design based on TI SLVA372D. Efficiency is a user estimate: D = 1 − ηVin/Vout and IL,avg = Iout/(1 − D). This efficiency-adjusted duty is a sizing approximation, not a device-specific switching simulation. The diode drop contributes to the displayed diode loss and switch voltage check, not an additional duty-cycle correction.
The initial inductance follows TI: ΔIestimate = ripple ratio × Iout × Vout/Vin,nom; L = Vin,nom(Vout − Vin,nom)/(ΔIestimate fs,min Vout). Enter the actual part value before finalising a design. Current screening uses Lmin = L(1 − tolerance) and fs,min. Inductance reduction under DC current, temperature and saturation must be included in the effective minimum value you choose.
CCM requires Ivalley > 0. The boundary output load is ΔIL(1 − D)/2. Boundary/DCM operation and synchronous forced reverse-current operation are not solved. If any point in the checked range leaves CCM, range-wide current and capacitor results are withheld. The waveform is shown only for a selected point in CCM.
Capacitors and ripple
Ceff = Cnom × (1 − tolerance) × retained fraction. Retention is taken from the selected capacitor's voltage and temperature data; it is not inferred from an X5R/X7R label. Enter complete-bank capacitance, ESR and RMS ratings. A value of zero for the bank means sizing only.
Output-capacitor charge swing is integrated from −Iout during on-time and IL − Iout during off-time. This equals Iout D/fs when the entire off-time inductor current exceeds the load, and includes the additional discharge when the valley falls below Iout. Cmin = charge swing / capacitive ripple budget. Output ESR ripple is bounded by ESR × Ipeak. The sum of capacitive and ESR ripple is a conservative upper bound, since their extrema need not coincide; ESL spikes are excluded.
Input capacitance uses ΔIL/(8 fs ΔVin), assuming the source supplies average input current and the capacitor carries the triangular AC component. The displayed minimum is the larger of this estimate and the IC datasheet minimum. Source impedance, cable inductance, start-up and load transients can demand substantially more capacitance. Output capacitance must also stay within the IC's compensation/stability recommendations.
Rating checks and range screening
The input range is sampled at 201 evenly spaced voltages plus the nominal input, Vin = Vout/(2η) (maximum ripple), and Vin = 2Vout/(3η) (maximum CCM boundary), when inside the range. Component extrema other than these analytical points are screening estimates. Checks apply at the entered load and constant efficiency, not a full load/temperature sweep.
Current-limit ceiling = (Ilim,min − ΔIL/2)(1 − D), for peak-current-limited ICs and only where the limit can support CCM. This excludes thermal limits, start-up and protection behaviour. A saturation-current check at operating peak does not certify survival at the maximum IC current limit.
Shortest on-time = Dmin/fs,max; shortest off-time = (1 − Dmax)/fs,max. Compare with guaranteed worst-case IC limits. Switch voltage is screened against Vout + Vf; diode reverse voltage against Vout. Voltage-rating passes cover steady state only; additional transient and ringing headroom is required. Unspecified ratings remain unchecked.
Total estimated loss = Pout(1/η − 1). Winding I²R, capacitor ESR and diode losses are a partial breakdown of that budget, never added to it. MOSFET conduction/switching loss, inductor core loss and thermal behaviour are not separately modelled.
References
- TI SLVA372D — Basic Calculation of a Boost Converter's Power Stage, revised November 2022.
- Analog Devices — How to Select a Boost Regulator/Controller IC, March 2021.