RC Filter Design: Choosing R and C for Low-Pass and High-Pass Filters

A cutoff frequency does not uniquely specify an RC filter. A 1 kΩ resistor with 100 nF and a 10 kΩ resistor with 10 nF have the same ideal pole, but they load the source differently and behave differently at an ADC input. Start with the frequency response you need, then check the surrounding circuit. ^{[1, 3]}

Low-pass or high-pass?

A low-pass has a series resistor and a capacitor from the output to ground; it preserves DC and attenuates high frequencies. A high-pass puts the capacitor in series and the resistor from output to ground; it blocks DC. For an ideal voltage source and an unloaded output, both have τ = RC and f_c = 1/(2πRC). At that frequency the voltage magnitude is 1/√2 of the passband value, or −3.0103 dB. ^[1]

Far beyond the pole, the low-pass falls by approximately 20 dB per decade; the high-pass has that slope below its pole. These are first-order responses, with a gradual transition. A cutoff alone cannot show whether unwanted frequencies receive enough attenuation. ^[2]

Worked example: 1 kΩ and 100 nF

Use R = 1,000 Ω, C = 100 × 10⁻⁹ F, no source resistance and no load. Then τ = 100 µs and f_c = 1,591.55 Hz. The following values come directly from the two transfer functions:

Try the low-pass example and inspect gain and phase →

Switch to the corresponding high-pass example →

Source and load resistance change the result

For the low-pass, let R_T = R + R_S and connect a resistive load R_L from output to ground. Circuit reduction gives a DC gain of R_L/(R_T + R_L) and τ = (R_T ∥ R_L)C. The pole is measured relative to this reduced passband.

Add a 10 kΩ load to the 1 kΩ / 100 nF example: DC gain becomes 10/11 = 0.9091, and the pole rises to 1,750.70 Hz. At the pole, the absolute gain is 0.6428, or approximately −3.838 dB relative to the source. A source resistance of 1 kΩ with no load instead doubles the time constant and lowers the pole to 795.77 Hz.

Check the loaded example →

For the high-pass topology used in the calculator, the output resistor and external load combine as R_P = R ∥ R_L. Its high-frequency gain is R_P/(R_S + R_P), and τ = (R_S + R_P)C. Enter the source and load explicitly before choosing standard parts.

Check tolerances and settling

For an unloaded ideal circuit, independently bounded R = 1 kΩ ±1% and C = 100 nF ±10% put the cutoff between 1,432.54 and 1,786.25 Hz. These are worst-case product corners, not a statistical distribution. A nominal 1.59 kHz filter therefore needs margin if an attenuation requirement is tight.

The ideal low-pass step error decays as e^−t/τ. A full-span step settling below ½ LSB of a 12-bit converter needs t ≥ τ ln(8,192), or 901.09 µs for τ = 100 µs. This simple calculation describes the external filter reaching its final value; a switched SAR input has its own sample capacitor and acquisition window. ^[3]

A large shunt capacitor can supply sampling charge, but it also has to recharge through the source between samples. Use the ADC input checker with the actual sampling-switch resistance and capacitance from the device datasheet. A passive filter does not automatically satisfy acquisition timing or provide enough anti-alias attenuation. ^[4]

Check the selected filter against an ADC acquisition window →

Tools used in this guide

• RC Low-Pass & High-Pass Filter Calculator – Passive RC low-pass and high-pass filters with source/load resistance, standard component selection, tolerance bounds and interactive gain and phase plots.
• ADC Input Settling Checker – SAR ADC source and RC filter settling during acquisition, filter-node recovery, and an optional DC accuracy budget for offset, gain, reference, INL and quantisation.
• Active Filter Designer – Sallen-Key and MFB low-pass and high-pass filters to 8th order (Butterworth, Bessel, Chebyshev): component values, standard-value response, and op amp GBW and slew-rate requirements.

Sources

1. Analog Devices University, An Introduction to Electrical Filters: passive RC topologies and frequency response.
2. Analog Devices, A Filter Primer: poles, filter order and practical response characteristics.
3. Texas Instruments SBAA178, Determining Minimum Acquisition Times for SAR ADCs: input resistance, sample capacitance and settling.
4. Texas Instruments SPRACZ0A, Charge-Sharing Driving Circuits for C2000 ADCs: external filter capacitors and sample-capacitor charge sharing.

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