Via Stub Resonance: How Long a Stub Can Be, and When to Back-Drill

The unused part of a through via below the layer where the signal leaves is an open-ended stub, and it resonates where it is a quarter wavelength long, at f ≈ c / (4 · L · √εeff), cutting a notch into the insertion loss of the channel. Keep that notch well above the signal's Nyquist frequency – this guide uses Simonovich's rule of putting the first null at seven times the Nyquist frequency or higher ^[1] – and where the stub is too long, back-drill it, use blind vias, or leave the via on the layer nearest the far side of the board.

The sections below give the formula and its uncertain input, a worked example on a 1.6 mm six-layer board, the longest stub per interface, and what the TI, Samtec and fabricator documents say about the 15 mil rule and back-drilling. All numbers come from the same formula as the Differential Via tool.

Why a via stub resonates

A signal that changes layer through a plated through hole uses only the part of the barrel between the two layers it connects. The rest of the barrel, down to the far surface of the board, is a short transmission line with an open end. The wave that runs into it is reflected at the open end and returns to the junction. When the round trip through the stub equals half a cycle, the returning wave cancels the through signal, and the insertion loss shows a deep null at that frequency. ^[1]

Longer stubs resonate at lower frequencies and increase insertion loss; TI notes that in most cases the stub portion of a via degrades the signal more than the part that carries it. ^{[3, 4]} Samtec's dense-BGA comparison shows the effect: the differential insertion loss of a via with a stub of about 60 mil falls away steeply above about 10 GHz, while the same via with a stub of about 10 mil stays within about 1.3 dB up to 30 GHz. ^[5]

The formula and which εr to use

f_stub = c / (4 × L_stub × √εr)

This is the quarter-wave condition, with c the speed of light and L_stub the length of unused barrel. It is the expression the Differential Via tool uses for its stub line, with the laminate εr you enter. ^{[1, 8]} It assumes that the stub behaves as a uniform open line in a homogeneous dielectric, and it ignores the loading of the pads, the antipads and the planes the barrel passes through.

That loading is the uncertain part. For a backplane with a measured null, Simonovich found an effective Dk of 6.16, against a published bulk Dk of 3.65 for the laminate. He attributes the difference to the via pad capacitance and to anisotropy: data sheets give the dielectric constant measured perpendicular to the laminate, glass-reinforced laminates are 15–25 % anisotropic, and in an earlier study the in-plane Dk had to be 18 % higher to match measurement. ^[1] A ratio of 6.16 / 3.65 lowers the resonance by 23 %. This guide therefore gives two values: the laminate εr of 4.2 (the tool default), and a pessimistic εeff of 7.1, which is 4.2 scaled by the same ratio.

As a check, TI's Gen5 note works the same calculation backwards: a 12 ps edge needs about 29 GHz of bandwidth, and the quarter wavelength at 29 GHz is about 54 mil in Megtron 6 (εr ≈ 3.4) and about 51 mil in FR-4 (εr ≈ 4.2). ^[2] The formula above gives 55.2 mil and 49.6 mil, within 3 % of TI's figures.

How much margin: the 7 × Nyquist rule

L_max = c / (4 × 7 × f_N × √εr)

Simonovich aims for an interconnect bandwidth of five times the Nyquist frequency f_N. Because the quarter-wave null acts as a notch filter, he places the first null at the 7th harmonic of the Nyquist frequency or higher, which keeps the 5th harmonic intact. ^[1] Solving the quarter-wave formula for that frequency gives the longest stub above. He also reports that the rule is conservative for NRZ: in a 28 Gb/s simulation, 12 mil stubs closed the eye height by only 17 mV (1.5 %) more than 5 mil stubs, with no extra jitter. Rules of thumb like this one help with planning, but they should never be used to sign off a high-speed design. ^[1]

The other published criteria differ, in both directions:

• TI's Gen5 note keeps a stub that is not back-drilled shorter than a quarter wavelength at the 29 GHz bandwidth of a 12 ps edge, which is 1.8 times the 16 GHz Gen5 Nyquist frequency. ^[2]
• Samtec rates stubs up to 80 mil as no problem at PCIe Gen3, says optimisation may help from 50 mil at Gen4, and expects every via to be simulated at Gen5. ^[5]At εr 4.2, 80 mil resonates at 4.5 times the Gen3 Nyquist frequency, and 50 mil at 3.6 times the Gen4 one.
• TI's general layout guides set one fixed limit for every interface: keep via stubs under 15 mil, and back-drill longer ones. ^{[2, 3, 4, 6]}

Worked example: a 1.6 mm six-layer board

The example uses the 1.6 mm six-layer “1080 prepreg · core 0.1/0.7 mm” stackup from the site's library: L1, 0.076 mm 1080 prepreg, L2, 0.10 mm core, L3, then 7628 prepreg, a 0.7 mm core and 7628 prepreg, then L4, 0.10 mm core, L5, 1080 prepreg and L6, 1.604 mm from copper to copper. With L2 and L5 as ground, L1, L3, L4 and L6 are signal layers (S-G-S-S-G-S). A pair enters at L1, for example from a BGA ball or a surface-mount connector, and leaves on L3, L4 or L6. The stub is the barrel from the far side of the exit-layer copper to the outer surface of L6.

Open the six-layer stackup in the Stackup tool →

L3 is the inner layer closest to the top, so a pair from L1 to L3 leaves almost the whole barrel unused. At εr 4.2 its null at 26.8 GHz is 6.7 times the Gen3 Nyquist frequency – just short of the 7 × rule, but well inside Samtec's 80 mil. At Gen4 it is only 3.4 times the Nyquist frequency, and at Gen5 the null sits below TI's 29 GHz, so for Gen4 and Gen5 this transition needs back-drilling or a different layer. With εeff 7.1 the margins shrink to 5.2, 2.6 and 1.3 times.

L4 sits next to the far side, so its stub of 8.9 mil is already under TI's 15 mil without back-drilling, and its null stays above 7 × Nyquist even for Gen5 (10.1 times at εr 4.2, 7.8 times at εeff 7.1). L6 uses the whole barrel and has no stub, but puts the pair on an outer layer. The rule is symmetrical: a pair entering from the bottom and leaving on L3 has the short stub instead.

Load the L1 → L3 transition (1.36 mm stub, 26.9 GHz) →

Load the L1 → L4 transition (0.23 mm stub, 159 GHz) →

Load the L1 → L6 transition (no stub) →

The rounded inputs give 26.9 GHz and 159 GHz in the tool. To see the pessimistic case, enter εr = 7.1; the tool then reports 20.7 GHz for the L3 stub, but it also uses that εr for the via impedance, so read only the stub line from that run.

Load the L1 → L3 stub with εeff = 7.1 →

The longest stub per interface

The Nyquist frequencies below are those of the Interface Rules data, half the NRZ line rate. ^[9] The last two rows are the 10 Gb/s and 28 Gb/s NRZ channels of Simonovich's article. L_max follows from the 7 × Nyquist rule; the last column quotes the via rule that the Interface Rules tool shows, with the document it comes from.

TI's 15 mil puts the null at 96 GHz at εr 4.2: inside the 7 × rule for every interface in the table except PCIe Gen5 and 28 Gb/s, where it reaches 6.0 and 6.9 times the Nyquist frequency. The 65 mil channel that measured an open eye at 10 Gb/s is longer than the 7 × rule allows, which is consistent with Simonovich's note that the rule is conservative for NRZ. ^[1] For PCIe Gen5 the rule and TI's 15 mil agree on the practical answer: short stubs by layer choice or back-drilling, and simulation of the actual via. ^{[2, 5]}

Check the PCIe Gen5 via and stub rules →

Back-drilling

Back-drilling removes the plating of the stub section after the board has been plated, with a drill bit slightly larger than the one that made the original hole. TI asks for it wherever a via transition leaves a stub longer than 15 mil, to reduce insertion loss and keep the stub from resonating. ^{[2, 3, 4]} Because it is a controlled-depth drilling step, the stub is never removed entirely:

• Simonovich puts the shortest practical back-drilled stub at 5 to 10 mil. ^[1]
• Sierra Circuits says the back-drill should bring the stub down to 10 mil, and that 2 to 3 mil stubs may be possible on the latest drilling equipment; check with your manufacturer. ^[7]
• Its recommended values: controlled-depth tolerance ±2 mil, back-drill 8 mil larger than the primary drill (10 mil preferred), 10 mil from back-drill to copper and 6 mil between back-drills. ^[7]
• Cost rises with the number of back-drilled vias and as the allowed residual stub gets shorter. ^[7]

A residual stub of 10 mil resonates at 144 GHz at εr 4.2, above the 112 GHz that the 7 × rule asks for at PCIe Gen5, and at 111 GHz with εeff 7.1, just at that limit. The larger back-drill hole also needs its clearance on every layer it passes through, so plan antipads and nearby traces for the back-drill diameter rather than the finished hole.

Alternatives to back-drilling

• Choose the exit layer. TI's example compares a 10-layer via from L3 to L10 (long stub, to be back-drilled) with one from L1 to L8 (stub of 15 mil or less). ^[3] In the six-layer example, moving the pair from L3 to L4 shortens the stub from 53.6 mil to 8.9 mil. Through vias that run from the top to the bottom layer have no stub at all. ^[1]
• Route on the outer layers. TI's Gen5 note recommends routing high-speed traces on the top or bottom layer only, and back-drilling when vias are needed. ^[2] For a through-hole receptacle, TI connects the pair on the bottom layer so that the pin is part of the signal path instead of a stub. ^[3]
• Blind, buried and laser-drilled vias do not leave a stub beyond the layers they connect. Simonovich and Sierra Circuits both list them as alternatives; Sierra Circuits adds that they are not always viable for manufacturing or cost reasons. ^{[1, 7]}
• Via-in-pad is not a stub fix. TI recommends via-in-pad instead of a via in an extended pad because it reduces the pad inductance. ^[2] It changes where the via sits, not how much barrel remains below the exit layer.
• Remove unused pads and enlarge antipads. TI does not permit non-functional pads on high-speed vias, and asks for antipads as large as possible on every layer (30 mil gives significant benefit) to reduce the via capacitance. ^{[2, 3, 4]} Pad capacitance is one reason the effective εr of a stub exceeds the laminate value. ^[1]

Shorter is not automatically better in a dense BGA field. TI and Samtec both note that a short stub reflects less but couples more crosstalk into neighbouring vias, so a long-stub and a short-stub breakout should be compared by simulation, including crosstalk, when back-drilling is not possible. ^{[2, 5]}

Checklist

1. For every layer change, measure the stub from the exit layer to the far end of the barrel, using the fabricator's stackup.
2. Calculate f_stub = c / (4 × L × √εr) with the laminate εr, and again with a value about 70 % higher as the pessimistic case.
3. Compare with the Nyquist frequency of the interface: aim for seven times; TI's 15 mil and the interface rules give the vendor limits.
4. If the stub is too long, first move the pair to the layer nearest the far side, then consider blind vias or back-drilling.
5. For back-drilling, agree the residual stub, depth tolerance and back-drill clearance with the fabricator before routing.
6. At PCIe Gen5 and similar rates, simulate the actual via, including crosstalk; do not sign off on a rule of thumb.

For the rest of a PCIe channel, see the PCIe routing guidelines and the Gen3 carrier-card case study; for choosing the layer order that decides the stub lengths, see how to choose a PCB stackup.

Tools used in this guide

• Differential Via – Via-pair differential impedance through the plane clearance from a 2D field solution, antipad sizing for a target, stub resonance and delay.
• Interface Design Rules – Impedance, skew, loss budget and length limits of PCIe, USB, Ethernet, HDMI, DDR and other interfaces, applied to a layer of your own stackup with the field solver.
• Layer Stack Manager – 178 rigid fab stackups plus six flex and rigid-flex design starters, with linked regions, editable materials and per-layer impedance.

Sources

1. B. Simonovich, “Via Stubs – Are They All Bad?”, Signal Integrity Journal, 10 March 2017: quarter-wave null, first null at the 7th harmonic of the Nyquist frequency, effective Dk 6.16 against a bulk Dk of 3.65, 5–10 mil back-drill residue, 270 mil and 65 mil measured channels, 5 mil against 12 mil stubs at 28 Gb/s.
2. Texas Instruments SNLA426, High-Speed PCB Layout for PCIe Gen 5 (June 2023), §21 Via Stubs, §22 Via Pads, §23 Via Discontinuity Mitigation (29 GHz bandwidth and the 51–54 mil quarter wave), §24 Back-Drill Stubs.
3. Texas Instruments SPRAAR7J, High-Speed Interface Layout Guidelines (November 2018, revised February 2023), §3.5 Connectors and Receptacles, §3.6 Via Discontinuity Mitigation, §3.7 Back-Drill Stubs, §3.8 Anti-Pad Diameter, Figures 3-4 to 3-6.
4. Texas Instruments SLLA414A, High-Speed Layout Guidelines for Signal Conditioners and USB Hubs (August 2025, revised January 2026), §4.5 Via Discontinuity Mitigation, §4.6 Back-Drill Stubs, §4.8 Anti-Pad Diameter.
5. S. Krooswyk, Samtec gEEk spEEk, Successful PCIe Interconnect Guidelines at 8, 16 and 32 GT/s (April 2021): slides “Via Design Considerations: Impedance”, “Stub vs. Xtalk” and “Placement”.
6. Texas Instruments SLAAE45, Layout Guidelines of PCIe Gen 4.0 Application With the TMUXHS4412 Multiplexer (September 2021), Table 2-1 and §2.3 Vias, Stub, and ESD/EMI Layout Guidelines.
7. Sierra Circuits, What is Back Drilling in PCB Design and Manufacturing? (29 December 2020): residual stub, Table 1 back-drill clearances and controlled-depth tolerance, cost, alternatives.
8. pcbplanner Differential Via, Method: the stub quarter-wave resonance c / (4 · L_stub · √εr).
9. pcbplanner Interface Rules: Nyquist frequency and via rules per interface, each with the document it was taken from.

Related guides

• PCIe PCB Routing Guidelines: Impedance, Return Paths, Vias, Loss and Skew
• PCIe Gen3 Routing on a Hobby Budget: Lessons from an M.2 NVMe Carrier Card
• How to Choose a PCB Stackup (and What 1080, 2116 and 7628 Mean)

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