Guides›Bob Smith Termination on Ethernet: the 75 Ω and 1000 pF Values, and Whether It Helps

Bob Smith Termination on Ethernet: the 75 Ω and 1000 pF Values, and Whether It Helps

Bob Smith termination connects each cable-side centre tap of the Ethernet magnetics through a 75 Ω resistor to one common node, and that node through a high-voltage capacitor — typically 1000 pF rated 2 kV — to chassis ground [7, 8]. It is meant to terminate the common mode of the cable pairs so that the cable radiates and picks up less [1]; every PHY data sheet and design guide checked here that shows the magnetics draws it, but whether 75 Ω is the right value, and whether the network makes a measurable difference at all, is disputed [2, 4].

This guide sets out what the patent claims, what the vendors draw and where they differ, the published critique, and what is safe to do on a board either way.

On this page

The circuit

A 1000BASE-T port has four transformers, one per pair. The windings on the cable side each have a centre tap, and the termination hangs off those four taps. The PHY-side taps are a separate matter: each goes to ground through its own 0.1 µF capacitor and is never tied to the others, because the common-mode voltage differs from pair to pair and with the speed mode [6, 7].

  • Cable-side centre taps: 4 × 75 Ω to a common node [6, 7, 8].
  • Common node: 1000 pF / 2 kV to chassis ground [7, 8].
  • PHY-side centre taps: 4 × 0.1 µF, one per tap, to signal ground [6, 7].

In magnetics with an auto-transformer stage (Microchip’s “12-core” type), the auto-transformer is what presents the low common-mode impedance into the termination; in “8-core” magnetics with the choke on the cable side, the 75 Ω connects to the transformer’s cable-side centre tap and the choke sits between it and the cable [9].

What the patent claims

Robert W. Smith filed the idea in January 1993; it issued as US 5,321,372 in June 1994 [1]. In outline:

  • Each twisted pair is terminated differentially in its matched input impedance, 100 Ω in the example.
  • The signals also produce common-mode currents, which set up standing waves on the cable; left unterminated, the cable becomes a common-mode radiator.
  • Terminating the common mode at both ends of the cable, in a load roughly equal to the pairs’ common-mode impedance, dissipates that energy. By reciprocity the cable also picks up less.
  • For Category 5 cable the patent gives the common-mode impedance as approximately 145 Ω, and the embodiment uses four 75 Ω resistors from the centre taps to a common node. Two 145 Ω resistors may be substituted for the four 75 Ω, and chokes may be used instead of resistors.

Two details are often missed. The patent states that the common node “could be, but does not necessarily have to be grounded”, and it does not mention a capacitor at all[1]. The 1000 pF / 2 kV capacitor in today’s vendor drawings is not from the patent; Microchip’s magnetics guide says plainly that the capacitor “is not a part of Bob Smith termination” but helps filter noise that leaks through the transformer [9]. The patent describes the benefit as “upwards of approximately 10 dB improvement in emissions and susceptibility”[1], but gives no measurement data or test conditions for that figure.

What the vendors draw

Every vendor document uses 75 Ω. The capacitor and its ground connection vary.

DocumentResistorsCapacitorNode returned to
Smith patent4 × 75 Ω, or 2 × 145 ΩNoneOptional ground [1]
Microchip KSZ9031RNX4 × 75 Ω1000 pF / 2 kVChassis ground [7]
Microchip VSC8541 guide (VPPD-04420)4 × 75 Ω1000 pF, 2 kVChassis ground [8]
Microchip magnetics guide (AN0098)75 Ω per pair1000 pF, 2 kVChassis ground; the capacitor is described as not part of the termination [9]
TI DP83867 data sheet4 × 75 Ω1 nF / 2 kVA ground joined to the PHY ground through a parallel R and C, with values deferred to TI’s schematic checklist [6]
TI AN-1469 (10/100 PHYTER)75 Ω each, the two unused pairs includedText: 1000 pF, at least 2 kV. Figure: 1500 pF, 2 kVChassis ground [5]
Satterwhite (critique)4 × 52.3 Ω for CAT5/5e, about 66 Ω for CAT6Not discussedNot discussed [2]

Four differences matter in practice:

  1. The capacitor value. 1000 pF is the common figure, but TI’s own PHYTER guide says 1000 pF in the text and draws 1500 pF in its schematic [5]. None of the documents explains how the value was chosen.
  2. Which ground. The Microchip documents and AN-1469 take the capacitor to chassis ground [5, 7, 8, 9]. The DP83867 figure draws a parallel R and C between the two grounds and leaves the values to a separate checklist [6].
  3. Unused pairs at 10/100 Mb/s. AN-1469 terminates the two unused pairs into the same node, and says the network also reduces susceptibility to noise from them[5].
  4. Power over Ethernet. TI’s PHYTER guide says Bob Smith termination does not apply to PoE [5]. Microchip keeps it, but isolates the resistors from the PoE DC voltage with blocking capacitors of about 10 nF, which it says is small enough not to disturb the pair-to-pair matching [9].

What the 1000 pF does

The capacitor’s reactance is X = 1 / (2π f C). For 1000 pF that is about 3.2 MΩ at 50 Hz, 159 Ω at 1 MHz, 16 Ω at 10 MHz and 1.6 Ω at 100 MHz. At mains frequency the node is effectively isolated from chassis; from about 10 MHz upward the capacitor is small next to the 75 Ω resistors, and the network behaves as a resistive termination to chassis.

Check the capacitor’s reactance at your frequency →

Because the capacitor connects the cable side of the transformer to chassis, it sits across the port’s isolation. Microchip quotes the IEEE requirement that a 10/100/1000BASE-T port withstand 1,500 V AC for one minute from each port to chassis ground [9]; 1500 V rms is about 2.1 kV peak. Every vendor document that states a rating specifies 2 kV, and TI’s PHYTER guide asks for at least 2 kV [5, 7, 8].

The critique: is 75 Ω the right value?

The best-known objection comes from Jim Satterwhite, written up as a Teltest engineer’s note and in EE Times in 2004; he says the work was done while he was at Cicada Semiconductor [2, 3]. His argument has three parts.

The 145 Ω figure is unsupported. Smith does not say which common-mode configuration has a 145 Ω impedance. Satterwhite measured CAT5 cable with a network analyser in three configurations [2]:

ConfigurationMeasured (CAT5)
One pair against one other pair, the remaining two floatingAbout 100 Ω
One pair against the other three tied togetherAbout 70 Ω
Two pairs tied against the other two tiedAbout 50 Ω

None is near 145 Ω, and he notes a variation of as much as ±15 % within a single cable [2]. One CAT6 cable gave 86.5 Ω for the one-against-three case [2].

Four 75 Ω resistors match the wrong impedance. Looking into one pair with the other three in parallel, the network presents R + R/3. With 75 Ω that is 100 Ω; to match the measured 70 Ω, R = 3 × 70 / 4 ≈ 52.5 Ω, for which he specifies 52.3 Ω [2]. His calculated common-mode return loss is 13.5–16.9 dB with 75 Ω against 28 dB to more than 40 dB with 52.3 Ω, over a 65–75 Ω range of cable impedance. For CAT6 he suggests about 66 Ω, and a compromise value where both cable types are expected [2].

A pulse test agrees. With 52.3, 75 and 100 Ω sets at both ends of a 7 ft cable and a common-mode pulse with about 1 ns rise time, the 75 Ω and 100 Ω terminations reflect visibly and 52.3 Ω does not [2].

Two limits of this work are worth stating. It measures reflection of a common-mode wave, not radiated emissions from a product. And Satterwhite himself says Smith’s technique “does reduce the common mode radiation, but not optimally”, and calls for more cable types to be characterised [2]. His theoretical section, using an estimated 200 Ω pair-to-pair impedance, gives R + R/3 = 200/3, which is 50 Ω rather than 52.3 Ω; the difference is small next to his ±15 % cable variation.

The critique: does it make any difference?

A second line of argument goes further. Measurements by Royce Bohnert are widely quoted for showing that 75 Ω, 52.3 Ω and no termination at all produced no apparent difference in return loss, in a comparison in the ~160 MHz marine band. We could not open Bohnert’s original presentation: Altium reports the original link as insecure, and the copy it points to returned an error when we tried it. This summary is therefore taken from Altium’s article [4], which should be read as a secondary source. The same article concludes that there is no reason not to fit the network, with either value, and suggests simulating the chosen choke and termination, capacitor included [4].

Neither side, in the documents we could open, publishes a radiated-emissions comparison of the same product with and without the network. The vendor documents draw the termination without presenting data on it: Microchip’s EMC table compares magnetics types, not termination values [9].

So does it help?

On the evidence available, the honest answer is that it is not shown either way. The patent claims a benefit, the vendors draw the circuit, one measured critique says the value is wrong for the impedance it is meant to match, and a second, available to us only second-hand, finds no difference in return loss at all.

Our recommendation: fit the network as your PHY vendor draws it — the parts cost little and every vendor drawing we found includes them — but treat the resistor value and the capacitor as variables, not as a specification. If a product fails radiated emissions on the cable, the termination is a cheap thing to vary during EMC testing, alongside the magnetics themselves.

Board-level rules that are not in dispute

  • Keep the PHY-side centre taps separate. Each gets its own 0.1 µF to ground; Microchip also advises against magnetics whose centre taps are ganged inside the part [6, 7, 9].
  • No metal under the magnetics on any layer; metal under an RJ45 with integrated magnetics is allowed [10].
  • Isolate chassis ground from the rest of the board with a keep-out of at least 20 mil on all layers, bridged only by a capacitor and a resistor of 1 MΩ or more [10]. Older TI guidance bridged it with two 1206 zero-ohm resistors either side of the RJ45, to be removed or replaced during certification testing [5]. The Bob Smith resistors connect to the cable side of the transformer, so they sit on the isolated side of the port together with the connector.
  • Size the capacitor for the isolation test. Every vendor document that gives a rating uses 2 kV; the port must survive 1500 V rms from the port to chassis [5, 9].
  • ESD protection on the PHY side. The connector side can see high common-mode voltage swings, and a protector placed there can fail during them [10].

The 20 mil keep-out is a layout rule; SNLA387 gives no voltage basis for it [10]. If a safety standard your product falls under sets a spacing for this barrier, work it out with the creepage and clearance calculator; the mains creepage guide explains the IEC 60664-1 terms it uses. Nothing in the Ethernet documents above specifies that standard for you.

Jacks with integrated magnetics

Many RJ45 jacks with built-in magnetics already contain the termination. Würth’s 7499111121A, a 1000BASE-T jack, has four 75 Ω resistors from the cable-side centre taps to a common node and a 0.001 µF / 2 kV capacitor inside the housing, brought out to a pin the data sheet labels GND (pin 10); its insulation test is 1500 V rms for one minute[11]. The 100BASE-TX 7499010211A has the same arrangement for two pairs, with the two unused pairs also terminated through 75 Ω, and a 0.001 µF capacitor to pin 8 [12].

With a jack like this:

  • Do not add a second network outside. It would sit in parallel with the one in the housing and halve the resistance.
  • Decide where the capacitor pin goes. The jack names it GND; the PHY documents above return the termination to chassis ground [7, 8, 9].
  • Read the schematic in the data sheet. Both Würth parts show the network there [11, 12]; check the part you use rather than assuming.

Integrated jacks save space but are not automatically better for EMC. Microchip notes that their magnetic cores are smaller and closer together, which can limit the choke’s effectiveness, against the benefit of the metal shield, and that emissions can be better or worse depending on the product [9]; and TI recommends a discrete transformer for better EMC performance with the DP83867 [6].

Checklist

  1. Four 75 Ω resistors from the cable-side centre taps to one node, unless you have measured a better value for your cable and magnetics.
  2. 1000 pF from that node to chassis ground, rated at least 2 kV.
  3. PHY-side centre taps separate, each with its own 0.1 µF to ground.
  4. With PoE, follow your PHY and PSE vendor; Microchip isolates the resistors from the PoE DC voltage with blocking capacitors of about 10 nF.
  5. Integrated-magnetics jack: check whether the network is already inside before adding one.
  6. Chassis island isolated by at least 20 mil on all layers; no metal under discrete magnetics; ESD parts on the PHY side.

See every 1000BASE-T layout rule with its source →

The impedance, pair-matching and length rules for the MDI traces themselves are in the interface rules tool, which applies them to your stackup.

Tools used in this guide

  • Interface Design Rules – Impedance, skew, loss budget and length limits of PCIe, USB, Ethernet, HDMI, DDR and other interfaces, applied to a layer of your own stackup with the field solver.
  • Reactance & LC Resonance – XL and XC at a frequency, LC resonance, the L or C for a target frequency, and series/parallel LC impedance with Q.
  • Creepage & Clearance (IEC 60664-1) – Minimum clearance and creepage per IEC 60664-1: impulse voltage from mains and overvoltage category, pollution degree, CTI material group, reinforced insulation, altitude.

Sources

  1. R. W. Smith, US Patent 5,321,372, “Apparatus and method for terminating cables to minimize emissions and susceptibility”, filed 8 January 1993, issued 14 June 1994.
  2. J. Satterwhite, “Bob Smith Termination vs Proper Termination”, Teltest Electronics Laboratories Engineer’s Notes, 30 January 2004 (Table 1, Figures 5–8, CAT6 section).
  3. J. Satterwhite, “Updating the Bob Smith termination technique”, EE Times, 30 April 2004.
  4. Z. Peterson, “Bob Smith Termination for Ethernet Circuits: Is it Correct?”, Altium Resources, 28 October 2020 (secondary summary of R. Bohnert’s measurements).
  5. Texas Instruments SNLA079D, AN-1469 PHYTER Design & Layout Guide, rev. April 2013 (Figure 2, §2.3, §2.4).
  6. Texas Instruments DP83867IR/CR data sheet SNLS484J, rev. June 2026 (Figure 9-2, §9.2.2.2.1).
  7. Microchip KSZ9031RNX data sheet DS00002117K (§12.0, Figure 12-1, Table 12-1).
  8. Microchip ENT-AN1231 VSC8541 Design and Layout Guide, VPPD-04420 Rev. 1.1, September 2017 (§3.1.3, Figure 2).
  9. Microchip ENT-AN0098 Magnetics Guide, VPPD-01740 Rev. 2.2, June 2018 (§2, §3.2–3.5, §3.8, §3.9, Figures 2 and 3).
  10. Texas Instruments SNLA387, Ethernet PHY PCB Design Layout Checklist, June 2021.
  11. Würth Elektronik 7499111121A WE-RJ45LAN data sheet, rev. 003.000, 2023-07-11 (1000BASE-T jack with integrated magnetics).
  12. Würth Elektronik 7499010211A WE-RJ45LAN data sheet, rev. 003.000, 2023-07-11 (100BASE-TX jack with integrated magnetics).

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