Thermal Via Arrays: Barrel Geometry, Filling and Temperature Drop
A thermal via conducts heat through its plated copper barrel; filling the hole adds a parallel conduction path. An array helps carry heat to other copper layers, but its vertical resistance is only part of the cooling problem. The package connection, lateral spreading and transfer to ambient still matter. [1, 2]
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Use the finished hole and the barrel plating
PCBPlanner models a straight, uniform tube through board thickness h. If d is the finished hole and t is the radial plating thickness, the outside diameter is d + 2t:
Lengths must be in metres and areas in square metres for thermal resistance in K/W, numerically equal to °C/W. The tool uses kCU = 401 W/(m·K). An open hole uses zero fill conductivity in this simplified model. The remaining laminate beneath the pad adds another parallel path:
ALAM excludes the outside cross-section of all barrels. The formula assumes a uniform temperature at each end of the array; it does not solve heat spreading within a real pad or plane.
Worked example: nine vias under a 3 mm pad
Take nine vias under a 3 × 3 mm pad, with 0.30 mm finished holes, 25 µm barrel plating, 1.6 mm board thickness and laminate conductivity of 0.3 W/(m·K). Assume 2 W passes through this modeled vertical path.
| Open-via quantity | Calculated value |
|---|---|
| One copper barrel | 156.316 °C/W |
| Nine barrels in parallel | 17.368 °C/W |
| Array plus laminate | 16.920 °C/W |
| Top-to-bottom drop at 2 W | 33.840 °C |
Load the nine-via example in the Thermal Via Array calculator →
Does filling the hole improve cooling?
Keeping that geometry fixed gives the following model results. The conductivities are illustrative calculator presets; use the fabricator's actual fill-material value when it is available.
| Fill | kFILL, W/(m·K) | Array + laminate, °C/W | Drop at 2 W, °C |
|---|---|---|---|
| Open | 0 | 16.920 | 33.840 |
| Non-conductive epoxy | 0.25 | 16.892 | 33.784 |
| Conductive epoxy | 3.5 | 16.531 | 33.062 |
| Copper | 401 | 4.576 | 9.152 |
In this example, low-conductivity epoxy barely changes the thermal resistance because the barrel dominates conduction. Filling can still serve an assembly purpose. A resin-filled, copper-capped via is not a solid copper-filled via: its core remains resin, and this model does not separately represent the cap.
Compare the same array with copper filling →
To keep the open-via result alongside your edits, use Compare in the Results header, then change fill or via count. Baseline A stays fixed while the current calculation updates.
A temperature drop is not a junction temperature
The 33.840 °C figure is the difference between the modeled top and bottom surfaces when the specified 2 W crosses that path. It is not the rise above ambient. Real heat can leave by several paths, and inner planes intercept heat before it reaches the bottom. Avoid adding this resistance to a measured or datasheet θJA that already includes the PCB path. [2]
Check the assembly and plane connections
Follow the package's exposed-pad dimensions, electrical connection and via recommendations. TI's PowerPAD guidance explains the importance of soldering the exposed pad, controlling solder loss into holes and connecting thermal vias solidly to planes. Confirm the fill, cap and stencil process with the assembler; the schematic via drawing does not calculate pitch or certify that the array fits. [1]
Check how the receiving copper spreads heat and transfers it to air →
Tools used in this guide
- Thermal Via Array – Thermal resistance of a via array under a hot pad, with plugged or filled vias, and the temperature drop through the board.
- Copper Area for Heat Spreading – How much copper a hot part needs: copper-pour thermal resistance by convection and radiation, junction temperature and the smallest pour for a Tj limit.
- Junction Temperature – Junction temperature from power and the thermal-resistance chain (θJA or θJC + θCS + θSA), and the maximum power for a Tj limit.
Sources
- Texas Instruments SLMA002H, PowerPAD Thermally Enhanced Package, sections 2.3 and 2.4: thermal lands, vias, plane connections and assembly.
- Texas Instruments SPRA953D, Semiconductor and IC Package Thermal Metrics: thermal-resistance definitions and the limitations of datasheet metrics.
Related guides
- How Much Copper Does a Regulator Need? PCB Heat Spreading in Numbers
- LDO Efficiency, Power Dissipation and Dropout: A Worked Thermal Check
- How Much Current Can a PCB Via Carry? Worked Examples for Power Rails
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